[Baypiggies] Guido's Blog: It isn't Easy to Remove the GIL

[Dennis Reinhardt]

At 08:55 PM 9/14/2007, Andy Wiggin wrote:
>DR> Ignoring threshold effects (a huge assumption), joint reductions in 
>voltage
> > and frequency yield a 3rd order (X**3) reduction in power.
>AW>I'm guessing that your assumptions are more in terms of moving from
>one process node to  the next, whereas the example I'm looking at (I'm
>pretty sure) is based on two thermally bound designs at the same
>
>AW>The example I'm looking at, the chip vendor reduces core vdd by 10%
>(1.2 -> 1.09) and core clock frequency by 30% (3.0GHz -> 2.3GHz) and
>this cuts power by 50%. This allows them to put two of these things
>(in essence, at least) in one package because there within the thermal
>budget.


Actually, no, I am not talking about different processes.

Circuit power (CMOS) is proportional to V**2f where V is voltage and f is 
operating frequency.  Where V is significantly greater than transistor 
threshold voltage (0.7 volts), then f is proportional to V and power is 
proportional to f**3, as I said above.

In the example you cite, working with CV**2f and substituting 10 and 30%, 
we see power reduction of .9**2 x .7 = .57, consistent with the 50% you 
cite allowing for the granularity of the numbers.

We are talking about the same basic situation.

Dennis
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| Dennis    | DennisR at dair.com    |
| Reinhardt | http://www.dair.com |
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