[pypy-svn] pypy arm-backed-float: some register allocation related fixes

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: arm-backed-float
Changeset: r43148:c8a2911e2b9b
Date: 2011-04-04 15:55 +0200
http://bitbucket.org/pypy/pypy/changeset/c8a2911e2b9b/

Log:	some register allocation related fixes

diff --git a/pypy/jit/backend/arm/assembler.py b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -710,6 +710,9 @@
             self.mc.PUSH([loc.value])
         elif loc.is_vfp_reg():
             self.mc.VPUSH([loc.value])
+        elif loc.is_imm():
+            self.regalloc_mov(loc, r.ip)
+            self.mc.PUSH([r.ip.value])
         else:
             assert 0, 'ffuu'
 

diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -214,7 +214,7 @@
             i += 1
             if loc.is_reg():
                 self.rm.reg_bindings[arg] = loc
-            elif loc.is_vfp_reg:
+            elif loc.is_vfp_reg():
                 self.vfprm.reg_bindings[arg] = loc
             else:
                 assert loc.is_stack()
@@ -264,8 +264,11 @@
             box = thing
         return loc, box
 
-
-
+    def _sync_var(self, v):
+        if v.type == FLOAT:
+            self.vfprm._sync_var(v)
+        else:
+            self.rm._sync_var(v)
 
     def prepare_op_int_add(self, op, fcond):
         boxes = list(op.getarglist())