I'm looking at using PyPy's flow object space for an experimental converter for MyHDL (http://www.myhdl.org/), a Python library for representing HDL (i.e. hardware) models. By conversion, I mean converting the MyHDL model that represents the hardware into either Verilog or VHDL that downstream tools will support. Currently, there is a converter that works very well in many situations, but there are substantial limitations on the code that can be converted (much greater restrictions than RPython imposes), as well as somewhat frustrating corner cases. It strikes me that much of the heavy lifting of the conversion problem can be handled by the PyPy stack. My question then regards the following. MyHDL represents certain low level structures as python objects. For example, there is a notion of a signal, represented by a Signal object, that has a one to one mapping to the target HDL language. All the attributes of the Signal object describe how it should be converted. So, during annotation, the Signal object should be maintained as a base type, rather than burying deeper into the object to try and infer more about its type (which invariably breaks things due to RPython non-conformity). There are probably a few other types (though not many) that should be handled similarly. How does one instruct the translator to do this? Is it a case of writing a custom TranslationDriver to handle the custom types? Thanks for any help, Henry