[ANN] Python as a test and modeling langauge for Verilog
Oroboro is an approach to using Python as a test and modeling language for Verilog. With it, Python generator functions are used to model simulation threads in a cooperative multitasking style. A simulation task in Python can suspend its execution with a yield statement that lists the reasons the task should be resumed. Typical reasons map directly to VPI callback reasons. Oroboro does not implement a scheduler of its own, rather, it relies on Verilog for all event scheduling through the use of callback functions. A short example illustrates some basic capabilities for interacting with a Verilog simulation.
from oroboro import *
def watcher(sig): print "Watching signal %s" % sig while 1:
yield sigchange(sig), timeout(10)
if isinstance(currentreason(), sigchange): print "New value for signal %s is %s" % (sig, sig.get())
if isinstance(currentreason(), timeout): print "Timeout has elapsed. Wait again."
s = signal("top.mysignal") t = task(watcher, s)
The example above illustrates a simple task that watches a Verilog signal. The task 'watcher' loops indefinitely, suspending its execution with a yield statement that lists the reasons it should be resumed. Here, the task waits until either the signal value changes, or a 10 simulation tick timeout occurs ... whichever comes first. When the task resumes, it uses the 'currentreason' function to determine whether the first or second reason in the yield statement was triggered. The task prints an informative message and then loops.
A longer paper discussing Oroboro, source downloads and examples can be found at: