I'm happy to announce the release of MyHDL 0.6. MyHDL is a Python package for using Python as a hardware description language. The highlight of this release is conversion to VHDL, in addition to the existing Verilog capability. Furthermore, the convertible subset has been broadened substantially beyond synthesizable logic, to support test bench conversion. For a complete overview, see: http://www.myhdl.org/doku.php/overview To check whether MyHDL can be useful to you, please read: http://www.myhdl.org/doku.php/why To find out the details of what's new in this release: http://www.myhdl.org/doc/0.6/whatsnew/0.6.html You can download the release from SourceForge: http://sourceforge.net/project/showfiles.php?group_id=91207 Best regards, Jan Decaluwe -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a hardware description language: http://www.myhdl.org
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Jan Decaluwe