I am pleased to announce the first alpha release of PyVHDL. What is PyVHDL? --------------- It is a VHDL simulator which translates VHDL processes to python bytecode. Standard Logic, and Standard Logic Vector types are implemented as python classes. Concurrent processes can be written in Python to create testbenches, or implement any complexity of logic design. These Python processes are seamlessly included in the simulations. PyVHDL includes a fork of the ZamiaCAD VHDL IDE for editing designs, and running simulations. ZamiaCAD also displays signal waveforms generated during the simulation. PyVHDL is able to simulate the Plasma 32 bit MIPS CPU design. All instruction tests run successfully, That said, not all VHDL language features are implemented at this time, hence the alpha designation. How can I learn more? -------------------- To try out PyVHDL, start at the documentation here: http://pyvhdl-docs.readthedocs.io/en/latest/ ----------------------- version: 0.0.1 ALPHA license: GNU General Public License Version 3 e-mail: pyvhdl@gmail.com