- all machines Python runs on should AFAIK be cache-coherent: CPUs synchronize their views of memory in a rather timely fashion.
Ok. I thought that Itanium was an example where this assumption is actually violated (as many web pages claim such a restriction), however, it seems that on Itanium, caches are indeed synchronized using MESI. So claims wrt. lack of cache consistency on Itanium, and the need for barrier instruction, seem to be caused by the Itanium feature that allows the processor to fetch memory out-of-order, i.e. an earlier read may see a later memory state. This is apparently used to satisfy reads as soon as the cache line is read (so that the cache line can be discarded earlier). Wrt. to your requirement ("rather timely fashion", this still seems to be fine). Still, this all needs to be documented in the code :-) Regards, Martin