On Wed, May 29, 2019 at 3:45 AM Greg Ewing firstname.lastname@example.org wrote: >
Yanghao Hua wrote:
a different assignment behavior in HDL is your assignment does not take effect until a delta cycle of zero virtual time has passed. (did you really looked at the previous postings? :)
You need to understand that most of the people reading this are not familiar with the workings and semantics of HDLs, so that phrases like "delta cycle of zero virtual time" are meaningless word salad. We need you to tell us what this new kind of assignment will do in Python terms.
It should do nothing in python terms, but rather let the user decide what to do. This is for representing ideas for a specific domain, if I explain in HDL terms, people complain python people cannot make sense out of it, if I explain in Python terms, people complain what problem are you trying to solve? So ... the short answer is this is the last thing python lacks of flexibility and would be great if python community are interested to support it.
x = 4 should be something like x <== 4 or x := 4 (the latter has been taken by the assignment expressions though ...). Such that variable initialization (=) and utilization (<==) can be differentiated.
Since you seem to be willing to use a different syntax for this kind of assignment, my suggestion is something like
x = Signal() ... x.next = 4
If I understand correctly what you want to use this for, that would be both suggestive of the semantics and entirely doable with existing Python features.
Yes sure this is doable, and this is exactly how I am doing it with python to interface verilog, e.g. signals are always accessed through module instances, and this is perfectly fine for verification. And there is another dozen different way to do this. But this is just not as intuitive as x <== 4 I am afraid. And for me this just kills all my motivation to use python to design hardware. If I use python to do something and I have to type more chars it doesn't make sense for me.