On Thu, May 30, 2019 at 12:50 AM Greg Ewing email@example.com wrote: >
Steven D'Aprano wrote:
Yanghao Hua wants to customise the behaviour of assignment. I believe that he wants to emulate the behaviour of some hardware description languages, where the equals sign = doesn't mean assignment (if I have understood correctly, which I may not have), but Something Else.
Maybe I can help a bit here. I don't have a deep knowledge of HDLs. but from what I gather, they typically have two different assignment-like operations. One of them is like assignment in a functional language, where you're defining a signal as a function of other existing signals. This corresponds to combinatorial logic in hardware. Python's existing assigment is fine for this, I think.
The other represents updating a signal when some event occurs, such as a clock transition. In hardware terms, it corresponds to changing the state of a flip-flop. The OP wants a new operator and associated dunder method to represent this operation. He doesn't want to override normal assignment.
That's basically right. And three small addition/correction: 1. Actually combinational logics can be modeled with both blocking and non-blocking logic. So one of them is enough already. 2. python's assignment is having very different semantics, so even for the verilog blocking assignment, which need to make the current "thread/process" to wait until the assignment finishes, is still not possible to model with python's assignment operator. 3. the signal change is really modeled on gate level, which are AND/OR/XOR/MUX gates. There are optimized flip-flop entities too but basically you can also build FFs from the primary gates. And the change of the signal, is actually just change the input of the FFs, not really the FF states itself. FF state change is modeled and inferred with a sensitivity list (a list of signals which triggers a thread/process to run) that has a clock.