On Sun, May 26, 2019 at 12:04 AM David Mertz firstname.lastname@example.org wrote: >
I don't really understand HDL/Verilog, but I've worked with people who do. In fact, I even wrote a pre-processor that transformed the same DSL to Python, C++, and Verilog.
In my mind, the HDL use case is FAR too narrow and specialized to warrant a new arrow operator, let an entirely new parser and semantics around arbitrary operators. There are several existing dunders that could plausibly be repurposed already (<<, <<=, <=, etc). Those might look sightly different than the verilog operators, but that's a very small price. In fact, just using attributes and assignment is an incredibly low bar too, and allows whatever overriding you wish.
Well, depends on how we define narrow ... you are writing probably this email on a HDL designed machine ... and the entire world is powered by HDL designed silicons. that is not small for me at all.
I just don't buy the idea that such a DSL can only be useful if it spells 'abc <== message' and useless if it spelled the same thing as 'abc <<= message'.
So you don't find this is confusing?
signal <<= 5 # does it mean left shifting signal or assigning 5 to signal??
I really do think it is confusing.