
Hi, I've been writing Verilog simulations for years, and tinkering with Python for years. In the last couple years I have been calling out to Python from Verilog simulations, which has been awesome. Just this week I tried twisted out for the first time to write a simple custom TCP server. It was a great experience and even though I still know next to nothing about twisted, I think I'm in love :-) Now I have a crazy idea. I'd like that Python code that my Verilog calls out to to use twisted. OK, actually I've already done that, my Verilog calls out to my that TCP server that I wrote. I had to spawn a thread and run the server in that thread so that the Verilog could continue to do stuff in parallel with the server. It's working great. The real crazy thing I want is for the Verilog to call out to a twisted TCP client as well. Again, I need the client and server to not block the Verilog. My first attempt was to run client and server in two separate threads. I start the server thread, then I start the client thread and only in the client thread do I call reactor.run(). It seems to not be working. Before I try to figure out why, I thought I might ask here if it even should work. Here's a different way to explain it, in case that helps: main thread is verilog which spawns server_thread def server_thread(): reactor.listenTCP(ServerFactory()) main thread spawns client_thread def client_thread() reactor.connectTCP(ClientFactory()) reactor.run() I read the page on threads in twisted and I'm guessing Would it be better to have the main thread just spawn one thread that does this? def client_server_thread(): reactor.listenTCP(...) reactor.connectTCP(...) reactor.run() Hmm, as I finish typing this all out, I'm realizing that surely someone has written at TCP proxy (essentially what this verilog simulation is doing) in twisted before. A quick internet search tells me yes...and of course they are not using threads. The way the whole verilog mess is written right now it would be much easier to use separate threads for client and server. Is that possible? If not I'll have to find a way to justify re-architecting the verilog mess. Thanks, Bryan