[CentralOH] Python -- Templates -- Specific Targets

James - Atlantix james at atlantixeng.com
Tue Oct 26 20:24:39 CEST 2010

For those not itereested in VHDL, there is a header template

which would show how to make a hader with Mako for general Python
programming below . . . . 



Issac; These are good comments however I have long ago evaluated MyHDL as
not appropriate for me. (It is essentially more or less geared towards
Verilog although it claims VHDL support & seems confusing layer on top of
these languages.)


I should be more specifica about my Mako usage. I am using is essentially in
the role of parser/linker in the chain of lex/parser/linker/compiler . . . .
I have a very comprehensive suite of self made VHDL libraries that I
intelligently assemble

with Mako, so Mako has lots of <$defs > inside the template. 


For example, lets say I wanted to build and array of 24 debouncer circuits.
I have a nice hierarchical, parameterized VHDL module for this. Mako does
look something like this:


debouncetemplate = Template("""

<%def name = "Debouncer(instance,enEN,enRST,EN,RST,DIN,DOUT)">

${instance} : entity work.debounce(rtl)

                port map(

                                CLK          => CLK,

                                HRST       => HRST,

        % if enEN:

                                EN      => ${EN},

        % else:

                EN      => '1',

        % endif 

        % if enRST:

                                RST_FF    => ${RST}, 

        % endif        

                                DIN     => ${DIN},

                                DOUT      => ${DOUT}  





Atlantixheader = Template("""

<%def name = "Header(module,fname,time,author,company)">


-- Module Name:  ${module}

--   File Name:  ${fname}

--     Created:  ${time}

--     Revised:  ${time}

--     Company:  ${company}

--      Author:  ${author}


--       Legal:  This software is coverered under the proprietary terms and
conditions of

--               Atlantix Engineering LLC. Not for use or reproduction by
third parties

--               outside of Atlantix Engineering. All Rights Reserved.




VHDLentity = Template("""

<%def name = "Header(entity,signals)">

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use ieee.numeric_std.all;


entity ${entity} is


                                 CLK           : in std_logic;

                 HRST     : in std_logic;

        % for (a,b) in signals:

                ${a}\t  : ${b}  

        % endfor


end ${entity};</%def>""")


from time import strftime



gendate = strftime("%m/%d/%Y at %H.%M hours")

print Atlantixheader.get_def("Header").render(module="Debouncer Array",

                                              fname="Debouncer Array.vhd",


                                              author="James Bonannno",



num_inputs = 10

vector_size = " std_logic_vector(%s downto 0)" % str(num_inputs-1)


print VHDLentity.get_def("Header").render(entity="DebouncerArray",signals =
(('EN','in std_logic;'),

('RST','in std_logic;'),




The programmatic generation would be like this:


for j in range(10):

    print Debouncetemplate.get_def("Debouncer").render(instance =

                                                       enEN = False,

                                                       enRST = False,




                                                       DOUT =






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