[Chicago] I thought translating to Fortran was a stretch...

Michael Tobis mtobis at gmail.com
Thu Jan 26 21:12:58 CET 2006

I think I'm being baited here, but OK, I'll take the bait.

Hiding Verilog under Python is indeed not that different of an idea
from hiding Fortran under Python.

In both cases you replace a machine-friendly language with an alliance
between a machine-friendly language and a programmer-friendly one.

Humans cannot easily tolerate the quantities of Verilog or Fortran
that contemporary projects call for, but our friend the Python will be
happy to take that on for us. We just have to feed our snake the right
abstractions and the right specifications, and stand back.

We get to work on a more interesting project and get the benefit of a
more robust output.


On 1/26/06, johnnnn <list at phaedrusdeinus.org> wrote:
> Apparently a Belgian EE/programmer has put out a python package which
> can be used as a hardware description/verification suite.
> http://www.eet.com/news/latest/showArticle.jhtml?articleID=177101584
> http://myhdl.jandecaluwe.com/doku.php
> Color me impressed.
> -johnnnnnnnnn
> _______________________________________________
> Chicago mailing list
> Chicago at python.org
> http://mail.python.org/mailman/listinfo/chicago

More information about the Chicago mailing list