[Chicago] I thought translating to Fortran was a stretch...

johnnnn list at phaedrusdeinus.org
Thu Jan 26 21:29:47 CET 2006


Not baited so much as gently and respectfully poked. :-)

I actually mostly wanted to point you in that direction in case, due to 
the similarity of effort, there was anything worth sharing with 
eachother. Pythonic synergy and all that.

And, well, mapping chips in Python is pretty cool, all things considered.

-johnnnnnnnnnn



Michael Tobis wrote:
> I think I'm being baited here, but OK, I'll take the bait.
>
> Hiding Verilog under Python is indeed not that different of an idea
> from hiding Fortran under Python.
>
> In both cases you replace a machine-friendly language with an alliance
> between a machine-friendly language and a programmer-friendly one.
>
> Humans cannot easily tolerate the quantities of Verilog or Fortran
> that contemporary projects call for, but our friend the Python will be
> happy to take that on for us. We just have to feed our snake the right
> abstractions and the right specifications, and stand back.
>
> We get to work on a more interesting project and get the benefit of a
> more robust output.
>
> mt
>
> On 1/26/06, johnnnn <list at phaedrusdeinus.org> wrote:
>   
>> Apparently a Belgian EE/programmer has put out a python package which
>> can be used as a hardware description/verification suite.
>>
>> http://www.eet.com/news/latest/showArticle.jhtml?articleID=177101584
>> http://myhdl.jandecaluwe.com/doku.php
>>
>> Color me impressed.
>>
>> -johnnnnnnnnn
>>
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>>     
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>   

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