[New-bugs-announce] [issue8613] Decimal module flags undetermined when a signal is trapped.
report at bugs.python.org
Tue May 4 16:54:01 CEST 2010
New submission from Mark Dickinson <dickinsm at gmail.com>:
In an effort to keep to one issue per tracker item, I'm pulling this issue out of the comments on issue 8567.
Issue: if a Decimal operation raises several signals, and one or more of those signals is trapped, how should that operation affect flags?
Decimal currently ends up setting some or none of those flags, depending on exactly which signal is trapped first.
Stefan points out that cdecimal and decnumber both treat all operations as atomic: *all* flags relevant to that operation are set, and only then are any traps acted on.
The specification isn't clear on this. At http://speleotrove.com/decimal/daexcep.html it says:
"""The value of the trap-enabler for each signal in the context determines whether an operation is completed after the condition is detected or whether the condition is trapped and hence not necessarily completed (see IEEE 754 §7 and §8)."""
There's also this (thanks, Stefan), in http://speleotrove.com/decimal/damodel.html
"""For each of the signals, the corresponding flag is set to 1 when the signal occurs. It is only reset to 0 by explicit user action."""
However, this doesn't really help: do we regard signals as being raised one-by-one during (or at the end of) an operation, or all at once? And should a trap take effect the moment a signal is handled, or should all traps be delayed until the end of an operation?
nosy: facundobatista, mark.dickinson, rhettinger, skrah
stage: unit test needed
title: Decimal module flags undetermined when a signal is trapped.
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