[pypy-svn] r18500 - in pypy/dist/pypy/translator/asm: . ppc test

[mwh at codespeak.net]

Author: mwh
Date: Wed Oct 12 18:49:07 2005
New Revision: 18500

Modified:
   pypy/dist/pypy/translator/asm/genasm.py
   pypy/dist/pypy/translator/asm/ppc/codegen.py
   pypy/dist/pypy/translator/asm/simulator.py
   pypy/dist/pypy/translator/asm/test/test_asm.py
Log:
test functions on the simulator after register allocation too.


Modified: pypy/dist/pypy/translator/asm/genasm.py
==============================================================================
--- pypy/dist/pypy/translator/asm/genasm.py	(original)
+++ pypy/dist/pypy/translator/asm/genasm.py	Wed Oct 12 18:49:07 2005
@@ -2,7 +2,7 @@
 from pypy.objspace.flow.model import traverse, Block, Variable, Constant
 from pypy.translator.asm import infregmachine
 from pypy.rpython.lltype import Signed
-from pypy.translator.asm.simulator import Machine
+from pypy.translator.asm.simulator import Machine, TranslateProgram
 
 #Available Machine code targets (processor+operating system)
 TARGET_UNKNOWN=0
@@ -57,6 +57,16 @@
                                       tracing=True)
 
         return r
+    elif processor == 'virtfinite':
+        insns = TranslateProgram(g.assembler.instructions, 50)
+        for i in insns:
+            print i
+        def r(*args):
+            return Machine.RunProgram(insns,
+                                      args,
+                                      tracing=True)
+
+        return r
     elif processor == 'ppc':
         from pypy.translator.asm.ppc import codegen
         return codegen.make_native_code(graph, g.assembler.instructions)

Modified: pypy/dist/pypy/translator/asm/ppc/codegen.py
==============================================================================
--- pypy/dist/pypy/translator/asm/ppc/codegen.py	(original)
+++ pypy/dist/pypy/translator/asm/ppc/codegen.py	Wed Oct 12 18:49:07 2005
@@ -1,4 +1,5 @@
 
+
 def make_native_code(graph, infreginsns):
     from pypy.translator.asm.ppcgen.func_builder import make_func
     maxregs = 0
@@ -8,10 +9,12 @@
         for r in insn.registers_used():
             maxregs = max(r, maxregs)
     
-    from pypy.translator.asm import regalloc
+    from pypy.translator.asm import regalloc, simulator
 
     insns = regalloc.regalloc(infreginsns, 30)
 
+    #insns = simulator.TranslateProgram(infreginsns, 5)
+
     codegen = PPCCodeGen()
 
     return make_func(codegen.assemble(insns), 'i',

Modified: pypy/dist/pypy/translator/asm/simulator.py
==============================================================================
--- pypy/dist/pypy/translator/asm/simulator.py	(original)
+++ pypy/dist/pypy/translator/asm/simulator.py	Wed Oct 12 18:49:07 2005
@@ -157,7 +157,7 @@
                     args.append('r%s=%s'%(arg, self._registers[arg]))
                 else:
                     args.append(arg)
-            #print opcode, ', '.join(map(str, args))
+            print opcode, ', '.join(map(str, args))
             #will want to trap later to defer unimplemented to the LLInterpreter...
         m = getattr(self,opcode,None)
         if m is not None:

Modified: pypy/dist/pypy/translator/asm/test/test_asm.py
==============================================================================
--- pypy/dist/pypy/translator/asm/test/test_asm.py	(original)
+++ pypy/dist/pypy/translator/asm/test/test_asm.py	Wed Oct 12 18:49:07 2005
@@ -121,6 +121,11 @@
         big = 1000000000
         assert f(big, big) == g(big, big)
         
+class TestAsmAfterAllocation(TestAsm):
+
+    processor = 'virtfinite'
+
+
 class TestAsmPPC(TestAsm):
 
     processor = 'ppc'