[pypy-svn] r34100 - in pypy/dist/pypy: jit/codegen/ppc translator/asm/ppcgen translator/asm/ppcgen/test

[niko at codespeak.net]

Author: niko
Date: Fri Nov  3 14:14:47 2006
New Revision: 34100

Modified:
   pypy/dist/pypy/jit/codegen/ppc/rgenop.py
   pypy/dist/pypy/translator/asm/ppcgen/rassemblermaker.py
   pypy/dist/pypy/translator/asm/ppcgen/test/test_rassemblermaker.py
Log:
(mwh,niko)

insert a simple prologue, uncovering an annoying annotation problem in the
meantime



Modified: pypy/dist/pypy/jit/codegen/ppc/rgenop.py
==============================================================================
--- pypy/dist/pypy/jit/codegen/ppc/rgenop.py	(original)
+++ pypy/dist/pypy/jit/codegen/ppc/rgenop.py	Fri Nov  3 14:14:47 2006
@@ -249,6 +249,11 @@
 
 RPPCAssembler = make_rassembler(MyPPCAssembler)
 
+r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, \
+    r13, r14, r15, r16, r17, r18, r19, r20, r21, r22, \
+    r23, r24, r25, r26, r27, r28, r29, r30, r31 = range(32)
+rSP = r1
+
 def emit(self, value):
     self.mc.write(value)
 RPPCAssembler.emit = emit
@@ -361,6 +366,12 @@
         self.initial_varmapping = {}
         for arg in self.inputargs:
             self.initial_varmapping[arg] = gprs[3+len(self.initial_varmapping)]
+
+        # Emit standard prologue
+        self.asm.mflr(r0)      
+        self.asm.stw(r0,rSP,8)
+        self.asm.stwu(rSP,rSP,-64)
+            
         return self.inputargs
 
     def _close(self):
@@ -388,7 +399,13 @@
         allocator = self.emit()
         reg = allocator.var2reg[gv_returnvar]
         if reg.number != 3:
-            self.asm.mr(3, reg.number)
+            self.asm.mr(r3, reg.number)
+
+        # Emit standard epilogue:
+        #   TODO rewrite to handle varying size stack?
+        self.asm.lwz(r0,rSP,64+8)
+        self.asm.mtlr(r0)
+        self.asm.addi(rSP,rSP,64)
         self.asm.blr()
         self._close()
 

Modified: pypy/dist/pypy/translator/asm/ppcgen/rassemblermaker.py
==============================================================================
--- pypy/dist/pypy/translator/asm/ppcgen/rassemblermaker.py	(original)
+++ pypy/dist/pypy/translator/asm/ppcgen/rassemblermaker.py	Fri Nov  3 14:14:47 2006
@@ -1,5 +1,5 @@
 from pypy.tool.sourcetools import compile2
-
+from pypy.rlib.rarithmetic import r_uint
 from pypy.translator.asm.ppcgen.form import IDesc, IDupDesc
 
 ##     "opcode": ( 0,  5),
@@ -32,19 +32,19 @@
     if isinstance(desc, IDupDesc):
         for destfield, srcfield in desc.dupfields.iteritems():
             fieldvalues.append((destfield, srcfield.name))
-    body = ['v = 0']
+    body = ['v = r_uint(0)']
     assert 'v' not in sig # that wouldn't be funny
     #body.append('print %r'%name + ', ' + ', '.join(["'%s:', %s"%(s, s) for s in sig]))
     for field, value in fieldvalues:
         if field.name == 'spr':
             body.append('spr = (%s&31) << 5 | (%s >> 5 & 31)'%(value, value))
             value = 'spr'
-        body.append('v |= (%3s & %#05x) << %d'%(value,
+        body.append('v |= (%3s & r_uint(%#05x)) << %d'%(value,
                                            field.mask,
                                            (32 - field.right - 1)))
     body.append('self.emit(v)')
     src = 'def %s(self, %s):\n    %s'%(name, ', '.join(sig), '\n    '.join(body))
-    d = {}
+    d = {'r_uint':r_uint}
     #print src
     exec compile2(src) in d
     return d[name]

Modified: pypy/dist/pypy/translator/asm/ppcgen/test/test_rassemblermaker.py
==============================================================================
--- pypy/dist/pypy/translator/asm/ppcgen/test/test_rassemblermaker.py	(original)
+++ pypy/dist/pypy/translator/asm/ppcgen/test/test_rassemblermaker.py	Fri Nov  3 14:14:47 2006
@@ -17,6 +17,7 @@
     def f():
         ra = RPPCAssembler()
         ra.add(3, 3, 4)
+        ra.lwz(1, 1, 1)  # ensure that high bit doesn't produce long but r_uint
         return ra.insts[0]
     res = interpret(f, [])
     assert res == add_r3_r3_r4
@@ -36,4 +37,3 @@
         a.mtctr(3)
         mrs.append(a.insts[0])
     assert mrs[0].assemble() == mrs[1]
-