[pypy-svn] r38069 - pypy/branch/new-jit-codegen/i386
arigo at codespeak.net
arigo at codespeak.net
Wed Feb 7 16:16:10 CET 2007
Author: arigo
Date: Wed Feb 7 16:16:09 2007
New Revision: 38069
Modified:
pypy/branch/new-jit-codegen/i386/operation.py
pypy/branch/new-jit-codegen/i386/regalloc.py
pypy/branch/new-jit-codegen/i386/rgenop.py
Log:
flexswitch() was not really fixed to work in this refactoring.
Modified: pypy/branch/new-jit-codegen/i386/operation.py
==============================================================================
--- pypy/branch/new-jit-codegen/i386/operation.py (original)
+++ pypy/branch/new-jit-codegen/i386/operation.py Wed Feb 7 16:16:09 2007
@@ -836,6 +836,21 @@
allocator.release(self.gv_value)
return opsource
+class OpGetExitSwitch(Op1):
+ # a bit of a hack: to put last in a block ending in a flexswitch,
+ # to load the switch value into a register and remember which
+ # register it is.
+ def generate(self, allocator):
+ op = allocator.get_operand(self.x)
+ if isinstance(op, REG):
+ self.reg = op
+ else:
+ self.reg = allocator.create_scratch_reg()
+ op = allocator.get_operand(self.x)
+ allocator.mc.MOV(self.reg, op)
+ allocator.end_clobber(self.reg)
+ allocator.release(self.x)
+
# ____________________________________________________________
def setup_opclasses(base):
Modified: pypy/branch/new-jit-codegen/i386/regalloc.py
==============================================================================
--- pypy/branch/new-jit-codegen/i386/regalloc.py (original)
+++ pypy/branch/new-jit-codegen/i386/regalloc.py Wed Feb 7 16:16:09 2007
@@ -52,15 +52,12 @@
# ----------
- def set_final(self, final_vars_gv):
- for v in final_vars_gv:
- self.using(v)
-
- def set_final_at_loc(self, final_vars_gv, locations):
+ def set_final(self, final_vars_gv, locations=None):
for i in range(len(final_vars_gv)):
v = final_vars_gv[i]
self.using(v)
- self.suggested_location[v] = locations[i]
+ if locations is not None:
+ self.suggested_location[v] = locations[i]
def compute_lifetimes(self):
for i in range(len(self.operations)-1, -1, -1):
@@ -421,8 +418,13 @@
self.clobber2(reg1, reg2)
def end_clobber(self, reg):
- assert isinstance(reg, REG)
- self.registers_free |= reg.bitmask
+ if isinstance(reg, REG):
+ bitmask = reg.bitmask
+ else:
+ assert isinstance(reg, REG8)
+ assert reg.op < 4
+ bitmask = reg.bitmask
+ self.registers_free |= bitmask
def clobber_cc(self):
v = self.cc_used_by
Modified: pypy/branch/new-jit-codegen/i386/rgenop.py
==============================================================================
--- pypy/branch/new-jit-codegen/i386/rgenop.py (original)
+++ pypy/branch/new-jit-codegen/i386/rgenop.py Wed Feb 7 16:16:09 2007
@@ -84,11 +84,11 @@
# ____________________________________________________________
class FlexSwitch(CodeGenSwitch):
- REG = eax
- def __init__(self, rgenop, graphctx, inputargs_gv, inputoperands):
+ def __init__(self, rgenop, graphctx, reg, inputargs_gv, inputoperands):
self.rgenop = rgenop
self.graphctx = graphctx
+ self.reg = reg
self.inputargs_gv = inputargs_gv
self.inputoperands = inputoperands
self.defaultcaseaddr = 0
@@ -142,7 +142,7 @@
end = self.endfreepos
mc = self.rgenop.InMemoryCodeBuilder(start, end)
value = gv_case.revealconst(lltype.Signed)
- mc.CMP(FlexSwitch.REG, imm(value))
+ mc.CMP(self.reg, imm(value))
targetbuilder.set_coming_from(mc, Conditions['E'])
pos = mc.tell()
assert self.defaultcaseaddr != 0
@@ -223,25 +223,22 @@
def start_writing(self):
self.paused_alive_gv = None
- def generate_block_code(self, final_vars_gv, force_vars=None,
- force_operands=None,
+ def generate_block_code(self, final_vars_gv, final_operands=None,
renaming=True):
if self.order_dependency is not None:
self.order_dependency.force_generate_code()
self.order_dependency = None
allocator = RegAllocator(self.operations)
- if final_vars_gv is not force_vars:
- allocator.set_final(final_vars_gv)
- if force_vars is not None:
- allocator.set_final_at_loc(force_vars, force_operands)
+ allocator.set_final(final_vars_gv, final_operands)
if not renaming:
+ assert final_operands is None
final_vars_gv = allocator.varsused() # unique final vars
allocator.compute_lifetimes()
allocator.init_reg_alloc(self.inputargs_gv, self.inputoperands)
mc = self.start_mc()
allocator.generate_operations(mc)
- if force_vars is not None:
- allocator.generate_final_moves(force_vars, force_operands)
+ if final_operands is not None:
+ allocator.generate_final_moves(final_vars_gv, final_operands)
#print 'NSTACKMAX==============>', allocator.nstackmax
self.graphctx.ensure_stack_vars(allocator.nstackmax)
del self.operations[:]
@@ -322,14 +319,14 @@
self.start_writing()
operands = targetlbl.inputoperands
assert operands is not None
- mc = self.generate_block_code(outputargs_gv, outputargs_gv, operands)
+ mc = self.generate_block_code(outputargs_gv, operands)
mc.JMP(rel32(targetlbl.targetaddr))
mc.done()
self.rgenop.close_mc(mc)
def finish_and_return(self, sigtoken, gv_returnvar):
gvs = [gv_returnvar]
- mc = self.generate_block_code(gvs, gvs, [eax])
+ mc = self.generate_block_code(gvs, [eax])
# --- epilogue ---
mc.MOV(esp, ebp)
mc.POP(ebp)
@@ -465,10 +462,10 @@
return op
def flexswitch(self, gv_exitswitch, args_gv):
- reg = FlexSwitch.REG
- mc = self.generate_block_code(args_gv, [gv_exitswitch], [reg],
- renaming=False)
- result = FlexSwitch(self.rgenop, self.graphctx,
+ op = OpGetExitSwitch(gv_exitswitch)
+ self.operations.append(op)
+ mc = self.generate_block_code(args_gv, renaming=False)
+ result = FlexSwitch(self.rgenop, self.graphctx, op.reg,
self.inputargs_gv, self.inputoperands)
default_builder = result.initialize(mc)
mc.done()
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