[pypy-svn] r53556 - in pypy/branch/gameboy-emulator/pypy/lang/gameboy: . test
cami at codespeak.net
cami at codespeak.net
Tue Apr 8 00:46:35 CEST 2008
Author: cami
Date: Tue Apr 8 00:46:33 2008
New Revision: 53556
Added:
pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_register.py
Modified:
pypy/branch/gameboy-emulator/pypy/lang/gameboy/cpu.py
pypy/branch/gameboy-emulator/pypy/lang/gameboy/interrupt.py
pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_cpu.py
Log:
added separated register testfile
improved tests
added more flag tests
completed several empty tests
fixed opCode assignment bug in cpu
fixed useCycles bug in registers
call and handlePendingInterrupts still non working
Modified: pypy/branch/gameboy-emulator/pypy/lang/gameboy/cpu.py
==============================================================================
--- pypy/branch/gameboy-emulator/pypy/lang/gameboy/cpu.py (original)
+++ pypy/branch/gameboy-emulator/pypy/lang/gameboy/cpu.py Tue Apr 8 00:46:33 2008
@@ -13,7 +13,7 @@
def set(self, value, useCycles=True):
self.value = value & 0xFF
- if (useCycles):
+ if useCycles:
self.cpu.cycles -= 1
def get(self, useCycles=True):
@@ -25,7 +25,7 @@
def sub(self, value, useCycles=True):
self.set(self.get(useCycles)-value, useCycles)
-# ___________________________________________________________________________
+# ------------------------------------------------------------------------------
class DoubleRegister(Register):
def __init__(self, cpu, hi=None, lo=None, resetValue=None):
@@ -54,7 +54,7 @@
self.setLo(lo, useCycles)
def reset(self):
- self.set(self.resetValue, None, False)
+ self.set(self.resetValue, None, useCycles=False)
def setHi(self, hi=0, useCycles=True):
self.hi.set(hi, useCycles)
@@ -63,27 +63,31 @@
self.lo.set(lo, useCycles)
def get(self, useCycles=True):
- return (self.hi.get()<<8) + self.lo.get()
+ return (self.hi.get(useCycles)<<8) + self.lo.get(useCycles)
def getHi(self, useCycles=True):
- return self.hi.get()
+ return self.hi.get(useCycles)
def getLo(self, useCycles=True):
- return self.lo.get()
+ return self.lo.get(useCycles)
def inc(self, useCycles=True):
- self.set(self.get() +1)
- self.cpu.cycles -= 1
+ self.set(self.get(useCycles) +1, None, useCycles)
+ if useCycles:
+ self.cpu.cycles -= 1
def dec(self, useCycles=True):
- self.set(self.get() - 1)
- self.cpu.cycles -= 1
+ self.set(self.get(useCycles) - 1, None, useCycles)
+ if useCycles:
+ self.cpu.cycles -= 1
def add(self, n=2, useCycles=True):
- self.set(self.get() + n)
- self.cpu.cycles -= 2
-
+ self.set(self.get(useCycles) + n, None, useCycles)
+ if useCycles:
+ self.cpu.cycles -= 2
+# ------------------------------------------------------------------------------
+
class ImmediatePseudoRegister(object):
def __init__(self, cpu, hl):
self.cpu = cpu
@@ -98,7 +102,9 @@
if not useCycles:
self.cpu.cycles += 1
return self.cpu.read(self.hl.get(useCycles))
-
+
+# ------------------------------------------------------------------------------
+
class FlagRegister(Register):
def __init__(self, cpu):
@@ -108,7 +114,7 @@
def reset(self, keepZ=False, keepN=False, keepH=False, keepC=False,\
keepP=False, keepS=False):
if not keepZ:
- self.zFlag = True
+ self.zFlag = False
if not keepN:
self.nFlag = False
if not keepH:
@@ -138,12 +144,12 @@
if useCycles:
self.cpu.cycles -= 1
- def zeroFlagAdd(self, a, reset=False):
+ def zFlagCompare(self, a, reset=False):
if (reset):
self.reset()
if isinstance(a, (Register)):
a = a.get()
- self.zFlag = (a==0)
+ self.zFlag = ((a & 0xFF) == 0)
def cFlagAdd(self, s, compareAnd=0x01, reset=False):
if (reset):
@@ -167,7 +173,7 @@
if a < b:
self.cFlag = True
-# ___________________________________________________________________________
+# # ------------------------------------------------------------------------------
class CPU(object):
"""
@@ -207,6 +213,7 @@
def reset(self):
self.resetRegisters()
self.f.reset()
+ self.f.zFlag = True
self.ime = False
self.halted = False
self.cycles = 0
@@ -329,8 +336,9 @@
def lowerPendingInterrupt(self):
for flag in self.interrupt.interruptFlags:
if flag.isPending():
- self.call(flag.callCode, disableIme=True)
+ self.call(flag.callCode, disableIME=True, useCycles=False)
flag.setPending(False)
+ return
# Execution
def fetchExecute(self):
@@ -371,14 +379,14 @@
self.popDoubleRegister(CPU.fetch, register)
# Stack, 2 cycles
- def push(self, data):
- self.sp.dec() # 2 cycles
- self.memory.write(self.sp.get(), data)
+ def push(self, data, useCycles=True):
+ self.sp.dec(useCycles) # 2 cycles
+ self.memory.write(self.sp.get(useCycles), data)
# PUSH rr 4 cycles
- def pushDoubleRegister(self, register):
- self.push(register.getHi()) # 2 cycles
- self.push(register.getLo()) # 2 cycles
+ def pushDoubleRegister(self, register, useCycles=True):
+ self.push(register.getHi(), useCycles) # 2 cycles
+ self.push(register.getLo(), useCycles) # 2 cycles
# 1 cycle
def pop(self):
@@ -398,13 +406,14 @@
self.cycles += 1
# 4 cycles
- def call(self, address, disableIME=False):
+ def call(self, address, disableIME=False, useCycles=True):
if disableIME:
self.ime = False
- self.push(self.pc.getHi()) # 2 cycles
- self.push(self.pc.getLo()) # 2 cycles
- self.pc.set(address) # 1 cycle
- self.cycles += 1
+ self.push(self.pc.getHi(useCycles), useCycles) # 2 cycles
+ self.push(self.pc.getLo(useCycles), useCycles) # 2 cycles
+ self.pc.set(address, useCycles) # 1 cycle
+ if useCycles:
+ self.cycles += 2
# 1 cycle
def ld(self, getter, setter):
@@ -423,7 +432,7 @@
# ALU, 1 cycle
def addA(self, getter, setter=None):
added = (self.a.get() + getter()) & 0xFF
- self.f.zeroFlagAdd(added, reset=True)
+ self.f.zFlagCompare(added, reset=True)
self.f.hFlagCompare(added, self.a)
self.f.cFlagCompare(added, self.a)
self.a.set(added) # 1 cycle
@@ -439,29 +448,30 @@
# 1 cycle
def addWithCarry(self, getter, setter=None):
- s = self.a.get() + getter();
+ data = getter()
+ s = self.a.get() + data
if self.f.cFlag:
s +=1
- self.carryFlagFinish(getter, 0x10)
- if s >= 0x100:
- self.f.cFlag= True
+ self.carryFlagFinish(s,data)
# 1 cycle
def subtractWithCarry(self, getter, setter=None):
- s = self.a.get() - getter();
+ data = getter()
+ s = self.a.get() - data
if self.f.cFlag:
s -= 1
- self.carryFlagFinish(getter, 0x10)
- if (s & 0xFF00) != 0:
- self.f.cFlag = True
+ self.carryFlagFinish(s, data)
self.f.nFlag = True
- def carryFlagFinish(self, getter):
+ def carryFlagFinish(self, s, data):
self.f.reset()
- self.f.zeroFlagAdd(s)
- if ((s ^ self.a.get() ^ getter()) & 0x10) != 0:
+ # set the hfalg if the 0x10 bit was affected
+ if ((s ^ self.a.get() ^ data) & 0x10) != 0:
self.f.hFlag = True
- self.a.set(s & 0xFF) # 1 cycle
+ if s >= 0x100:
+ self.f.cFlag= True
+ self.f.zFlagCompare(s)
+ self.a.set(s) # 1 cycle
# 1 cycle
def subtract(self, getter, setter=None):
@@ -473,7 +483,7 @@
s = (self.a.get() - getter()) & 0xFF
self.f.reset()
self.f.nFlag = True
- self.f.zeroFlagAdd(s)
+ self.f.zFlagCompare(s)
self.hcFlagFinish(s)
self.cycles -= 1
@@ -485,17 +495,17 @@
# 1 cycle
def AND(self, getter, setter=None):
self.a.set(self.a.get() & getter()) # 1 cycle
- self.f.zeroFlagAdd(self.a, reset=True)
+ self.f.zFlagCompare(self.a, reset=True)
# 1 cycle
def XOR(self, getter, setter=None):
self.a.set( self.a.get() ^ getter()) # 1 cycle
- self.f.zeroFlagAdd(self.a, reset=True)
+ self.f.zFlagCompare(self.a, reset=True)
# 1 cycle
def OR(self, getter, setter=None):
self.a.set(self.a.get() | getter()) # 1 cycle
- self.f.zeroFlagAdd(self.a, reset=True)
+ self.f.zFlagCompare(self.a, reset=True)
def incDoubleRegister(self, doubleRegister):
doubleRegister.inc()
@@ -516,7 +526,7 @@
def decIncFlagFinish(self, data, setter, compare):
self.f.reset(keepC=True)
- self.f.zeroFlagAdd(data)
+ self.f.zFlagCompare(data)
if (data & 0x0F) == compare:
self.f.hFlag = True
setter(data) # 1 cycle
@@ -579,14 +589,14 @@
# 2 cycles
def flagsAndSetterFinish(self, s, setter, compareAnd=0x01):
s &= 0xFF
- self.f.zeroFlagAdd(s, reset=True)
+ self.f.zFlagCompare(s, reset=True)
self.f.cFlagAdd(s, compareAnd)
setter(s) # 1 cycle
# 1 cycle
def swap(self, getter, setter):
s = ((getter() << 4) + (getter() >> 4)) & 0xFF
- self.f.zeroFlagAdd(s, reset=True)
+ self.f.zFlagCompare(s, reset=True)
setter(s)
# 2 cycles
@@ -709,7 +719,7 @@
self.f.reset(keepN=True)
if delta >= 0x60:
self.f.cFlag = True
- self.f.zeroFlagAdd(self.a)
+ self.f.zFlagCompare(self.a)
# INC rr
def incDoubleRegister(self, register):
@@ -812,8 +822,7 @@
# RETI 4 cycles
def returnFormInterrupt(self):
self.ret() # 4 cycles
- self.enableInterrupts()
- self.cycles += 1
+ self.enableInterrupts() # 1 cycle
# RST nn 4 cycles
def restart(self, nn):
@@ -827,8 +836,7 @@
# 1 cycle
def enableInterrupts(self):
self.ime = True
- self.cycles -= 1
- self.execute(self.fetch())
+ self.execute(self.fetch()) # 1
self.handlePendingInterrupt()
# HALT/STOP
@@ -875,7 +883,8 @@
opCode = 0x40
for storeRegister in GROUPED_REGISTERS:
for loadRegister in GROUPED_REGISTERS:
- opCodes.append((opCode, load_group_lambda(storeRegister, loadRegister)))
+ if loadRegister != CPU.getHLi or storeRegister != CPU.getHLi:
+ opCodes.append((opCode, load_group_lambda(storeRegister, loadRegister)))
opCode += 1
return opCodes
@@ -983,8 +992,7 @@
(0xA8, 0x01, CPU.XOR),
(0xB0, 0x01, CPU.OR),
(0xB8, 0x01, CPU.compareA),
- (0x06, 0x08, CPU.fetchLoad),
- (0x40, 0x01, CPU.resetBit, range(0, 8))
+ (0x06, 0x08, CPU.fetchLoad)
]
@@ -1013,8 +1021,8 @@
(0x28, 0x01, CPU.shiftRightArithmetic),
(0x30, 0x01, CPU.swap),
(0x38, 0x01, CPU.shiftWordRightLogical),
- (0x40, 0x01, CPU.testBit, range(0, 8)),
- (0xC0, 0x01, CPU.setBit, range(0, 8)),
+ (0x40, 0x01, CPU.testBit, range(0, 8)),
+ (0xC0, 0x01, CPU.setBit, range(0, 8)),
(0x80, 0x01, CPU.resetBit, range(0, 8))
]
Modified: pypy/branch/gameboy-emulator/pypy/lang/gameboy/interrupt.py
==============================================================================
--- pypy/branch/gameboy-emulator/pypy/lang/gameboy/interrupt.py (original)
+++ pypy/branch/gameboy-emulator/pypy/lang/gameboy/interrupt.py Tue Apr 8 00:46:33 2008
@@ -15,7 +15,7 @@
def isPending(self):
return self._isPending
- def setPending(self, _isPending):
+ def setPending(self, _isPending=True):
self._isPending = _isPending
Modified: pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_cpu.py
==============================================================================
--- pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_cpu.py (original)
+++ pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_cpu.py Tue Apr 8 00:46:33 2008
@@ -2,6 +2,7 @@
from pypy.lang.gameboy.cpu import *
from pypy.lang.gameboy.ram import *
from pypy.lang.gameboy import *
+from pypy.lang.gameboy.interrupt import *
class Memory(object):
def __init__(self):
@@ -13,136 +14,24 @@
def read(self, address):
return self.memory[address]
-def get_cpu():
- cpu = CPU(None, Memory())
- cpu.setROM([0]*0xFFFF);
- return cpu
+global TEST_CPU
-# ------------------------------------------------------------
-# TEST REGISTER
-def test_register_constructor():
- register = Register(get_cpu())
- assert register.get() == 0
- value = 10
- register = Register(get_cpu(), value)
- assert register.get() == value
-
-def test_register():
- register = Register(get_cpu())
- value = 2
- oldCycles = register.cpu.cycles
- register.set(value)
- assert register.get() == value
- assert oldCycles-register.cpu.cycles == 1
-
-def test_register_bounds():
- register = Register(get_cpu())
- value = 0x1234FF
- register.set(value)
- assert register.get() == 0xFF
-
-def test_reset():
- value = 0x12
- register = Register(get_cpu(), value)
- register.set(value+1)
- assert register.get() == value+1
- register.reset()
- assert register.get() == value
-
-# ------------------------------------------------------------
-# TEST DOUBLE REGISTER
+TEST_CPU = None
+def get_cpu(new=False):
+ if new:
+ cpu = CPU(Interrupt(), Memory())
+ cpu.setROM([0]*0xFFFF);
+ return cpu
+ global TEST_CPU
+ if TEST_CPU == None:
+ TEST_CPU = get_cpu(True)
+ TEST_CPU.reset()
+ return TEST_CPU
-def test_double_register_constructor():
- cpu = get_cpu()
- register = DoubleRegister(cpu)
- assert register.get() == 0
- assert register.getHi() == 0
- assert register.getLo() == 0
- value = 0x1234
- reg1 = Register(cpu)
- reg1.set(0x12)
- reg2 = Register(cpu)
- reg2.set(0x34)
- register = DoubleRegister(cpu, reg1, reg2)
- assert register.hi == reg1
- assert register.lo == reg2
- assert register.getHi() == reg1.get()
- assert register.getLo() == reg2.get()
-
-def test_double_register():
- register = DoubleRegister(get_cpu())
- value = 0x1234
- oldCycles = register.cpu.cycles
- register.set(value)
- assert oldCycles-register.cpu.cycles == 1
- assert register.get() == value
-
-def test_double_register_bounds():
- register = DoubleRegister(get_cpu())
- value = 0xFFFF1234
- register.set(value)
- assert register.get() == 0x1234
-
-def test_double_register_hilo():
- register = DoubleRegister(get_cpu())
- value = 0x1234
- valueHi = 0x12
- valueLo = 0x34
- oldCycles = register.cpu.cycles
- register.set(valueHi, valueLo)
- assert oldCycles-register.cpu.cycles == 2
- assert register.getHi() == valueHi
- assert register.getLo() == valueLo
- assert register.get() == value
-
- valueHi = 0x56
- oldCycles = register.cpu.cycles
- register.setHi(valueHi)
- assert oldCycles-register.cpu.cycles == 1
- assert register.getHi() == valueHi
- assert register.getLo() == valueLo
-
- valueLo = 0x78
- oldCycles = register.cpu.cycles
- register.setLo(valueLo)
- assert oldCycles-register.cpu.cycles == 1
- assert register.getHi() == valueHi
- assert register.getLo() == valueLo
-
-
-def test_double_register_methods():
- value = 0x1234
- register = DoubleRegister(get_cpu())
- register.set(value)
-
- oldCycles = register.cpu.cycles
- register.inc()
- assert oldCycles-register.cpu.cycles == 2
- assert register.get() == value+1
-
- oldCycles = register.cpu.cycles
- register.dec()
- assert oldCycles-register.cpu.cycles == 2
- assert register.get() == value
-
- addValue = 0x1001
- oldCycles = register.cpu.cycles
- register.add(addValue)
- assert oldCycles-register.cpu.cycles == 3
- assert register.get() == value+addValue
-
-
-def test_double_register_reset():
- value = 0x1234;
-
- register = DoubleRegister(get_cpu(), value)
- register.set(value+1)
- assert register.get() == value+1;
- register.reset()
- assert register.get() == value
# ------------------------------------------------------------
# TEST CPU
+
def test_getters():
cpu = get_cpu()
assert_default_registers(cpu)
@@ -350,6 +239,13 @@
pc += 1
cpu.rom[pc] = value & 0xFF
cpu.memory.write(pc, value & 0xFF)
+
+def test_prepare_for_fetch():
+ cpu = get_cpu()
+ value = 0x12
+ prepare_for_fetch(cpu, value+1, value)
+ assert cpu.fetch() == value
+ assert cpu.fetch() == value+1
def prepare_for_pop(cpu, value, valueLo=None):
sp = cpu.sp.get()
@@ -357,6 +253,13 @@
cpu.memory.write(sp, valueLo & 0xFF)
sp += 1
cpu.memory.write(sp, value & 0xFF)
+
+def test_prepare_for_pop():
+ cpu = get_cpu()
+ value = 0x12
+ prepare_for_pop(cpu, value+1, value)
+ assert cpu.pop() == value
+ assert cpu.pop() == value+1
def set_registers(registers, value):
#if registers is not list:
@@ -794,6 +697,8 @@
cpu = get_cpu()
value = 0x12
fValue = cpu.f.get()
+ cpu.f.nFlag = False
+ cpu.f.hFlag = False
cpu.a.set(value)
cycle_test(cpu, 0x2F, 1)
assert_default_registers(cpu, a=value^0xFF, f=None)
@@ -827,10 +732,11 @@
# halt
def test_0x76():
- py.test.skip("test not completed yet")
cpu = get_cpu()
+ cpu.cycles = 0xFF
+ cpu.ime = True
assert cpu.halted == False
- cycle_test(cpu, 0x76, 0)
+ cycle_test(cpu, 0x76, cpu.cycles)
assert cpu.halted == True
assert_default_registers(cpu)
@@ -857,6 +763,21 @@
opCode += 0x01
+def test_add_flags():
+ cpu = get_cpu()
+
+ cpu.a.set(0)
+ cpu.b.set(0)
+ cpu.addA(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=True, hFlag=False)
+
+ cpu.reset()
+ cpu.a.set(0x0F)
+ cpu.b.set(0x01)
+ cpu.addA(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=False, hFlag=True)
+
+
# add_A_B to add_A_A
def test_0x80_to_0x87():
cpu = get_cpu()
@@ -879,9 +800,44 @@
value += 3
opCode += 0x01
+
+def test_adc_flags():
+ cpu = get_cpu()
+ b = cpu.b
+ a = cpu.a
+
+ cpu.reset()
+ a.set(0)
+ b.set(0)
+ cpu.addWithCarry(b.get, b.set)
+ assert_default_registers(cpu, a=0, f=None)
+ assert_default_flags(cpu, zFlag=True, cFlag=False, hFlag=False)
+
+ cpu.reset()
+ a.set(0)
+ b.set(0)
+ cpu.f.cFlag = True
+ cpu.addWithCarry(b.get, b.set)
+ assert_default_registers(cpu, a=1, f=None)
+ assert_default_flags(cpu, zFlag=False, cFlag=False, hFlag=False)
+
+ cpu.reset()
+ a.set(0xF0)
+ b.set(0xFF)
+ cpu.addWithCarry(b.get, b.set)
+ # overflow for a
+ assert_default_registers(cpu, a=0xEF, bc=None, f=None)
+ assert_default_flags(cpu, zFlag=False, cFlag=True, hFlag=False)
+
+ cpu.reset()
+ a.set(0x0F)
+ b.set(0x01)
+ cpu.addWithCarry(b.get, b.set)
+ assert_default_registers(cpu, a=0x10, f=None, bc=None)
+ assert_default_flags(cpu, zFlag=False, cFlag=False, hFlag=True)
+
# adc_A_B to adx_A_A
def test_0x88_to_0x8F():
- py.test.skip("need a full flag checker imlementation")
cpu = get_cpu()
opCode = 0x88
value = 0x12
@@ -891,10 +847,24 @@
cpu.a.set(value)
register.set(value)
numCycles= 1
- if add == cpu.hli:
+ if register == cpu.hli:
numCycles = 2
cycle_test(cpu, opCode, numCycles)
assert cpu.a.get() == 2*value
+
+ cpu.reset()
+ cpu.f.cFlag = True
+ cpu.a.set(value-1)
+ register.set(value)
+ numCycles= 1
+ if register == cpu.hli:
+ numCycles = 2
+ cycle_test(cpu, opCode, numCycles)
+ if register == cpu.a:
+ assert cpu.a.get() == 2*value+1
+ else:
+ assert cpu.a.get() == 2*value
+
value += 3
opCode += 0x01
@@ -916,10 +886,82 @@
value += 3
opCode += 0x01
+def test_sbc_flags():
+ cpu = get_cpu()
+ b = cpu.b
+ a = cpu.a
+ value = 0xFF
+
+ cpu.reset()
+ a.set(value)
+ b.set(value)
+ cpu.subtractWithCarry(b.get, b.set)
+ assert_default_registers(cpu, a=0, bc=None, f=None)
+ assert_default_flags(cpu, zFlag=True, cFlag=False, hFlag=False, nFlag=True)
+
+ cpu.reset()
+ a.set(value)
+ b.set(value-1)
+ cpu.f.cFlag = True
+ cpu.subtractWithCarry(b.get, b.set)
+ assert_default_registers(cpu, a=0, bc=None, f=None)
+ assert_default_flags(cpu, zFlag=True, cFlag=False, hFlag=False, nFlag=True)
+
+ cpu.reset()
+ a.set(0x20)
+ b.set(0x01)
+ cpu.subtractWithCarry(b.get, b.set)
+ # overflow for a
+ assert_default_registers(cpu, a=0x1F, bc=None, f=None)
+ assert_default_flags(cpu, zFlag=False, cFlag=False, hFlag=True, nFlag=True)
+
+
# sbc_A_B to sbc_A_A
-def test_0x98():
- pass
+def test_0x98_0x9F():
+ cpu = get_cpu()
+ opCode = 0x98
+ value = 0x12
+ registers = [cpu.b, cpu.c, cpu.d, cpu.e, cpu.h, cpu.l, cpu.hli, cpu.a]
+ for register in registers:
+ cpu.reset()
+ cpu.a.set(value)
+ register.set(value)
+ numCycles= 1
+ if register == cpu.hli:
+ numCycles = 2
+ cycle_test(cpu, opCode, numCycles)
+ assert cpu.a.get() == 0
+
+ cpu.reset()
+ cpu.f.cFlag = True
+ cpu.a.set(value+1)
+ register.set(value)
+ numCycles= 1
+ if register == cpu.hli:
+ numCycles = 2
+ cycle_test(cpu, opCode, numCycles)
+ if register == cpu.a:
+ assert cpu.a.get() == 0xFF
+ else:
+ assert cpu.a.get() == 0
+
+ value += 3
+ opCode += 0x01
+def test_and_flags():
+ cpu = get_cpu()
+ value = 0x12
+ cpu.a.set(value)
+ cpu.b.set(value)
+ cpu.AND(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=False)
+
+ cpu.reset()
+ cpu.a.set(value)
+ cpu.b.set(0)
+ cpu.AND(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=True)
+
# and_A_B to and_A_A
def test_0xA0_to_0xA7():
cpu = get_cpu()
@@ -946,6 +988,21 @@
value += 1
opCode += 0x01
+
+def test_xor_flags():
+ cpu = get_cpu()
+ value = 0x12
+ cpu.a.set(value)
+ cpu.b.set(value)
+ cpu.XOR(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=True)
+
+ cpu.reset()
+ cpu.a.set(value)
+ cpu.b.set(value+1)
+ cpu.XOR(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=False)
+
# xor_A_B to xor_A_A
def test_0xA8_to_0xAF():
cpu = get_cpu()
@@ -972,6 +1029,20 @@
value += 1
opCode += 0x01
+def test_or_flags():
+ cpu = get_cpu()
+ value = 0x12
+ cpu.a.set(value)
+ cpu.b.set(value)
+ cpu.OR(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=False)
+
+ cpu.reset()
+ cpu.a.set(0)
+ cpu.b.set(0)
+ cpu.OR(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=True)
+
# or_A_B to or_A_A
def test_0xB0_to_0xB7():
cpu = get_cpu()
@@ -998,6 +1069,27 @@
value += 1
opCode += 0x01
+def test_cp_flags():
+ cpu = get_cpu()
+ value = 0x12
+ cpu.a.set(value)
+ cpu.b.set(value)
+ cpu.compareA(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=True, nFlag=True)
+
+ cpu.reset()
+ cpu.a.set(value)
+ cpu.b.set(0)
+ cpu.compareA(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=False, nFlag=True)
+
+ cpu.reset()
+ cpu.a.set(0xF0)
+ cpu.b.set(0x01)
+ cpu.compareA(cpu.b.get, cpu.b.set)
+ assert_default_flags(cpu, zFlag=False, hFlag=True, nFlag=True)
+
+
# cp_A_B to cp_A_A
def test_0xB8_to_0xBF():
cpu = get_cpu()
@@ -1136,20 +1228,23 @@
prepare_for_pop(cpu, value >> 8, value & 0xFF)
cycle_test(cpu, 0xC9, 4)
assert_default_registers(cpu, pc=value, sp=valueSp+2)
-
# reti
-def test_0xD9():
- py.test.skip("deeper knowledge necessary")
+def test_0xD9_returnFormInterrupt():
+ py.test.skip("cycle bug in cpu")
cpu = get_cpu()
value = 0x1234
+ cpu.sp.set(0)
prepare_for_pop(cpu, value >> 8, value & 0xFF)
prepare_for_fetch(cpu, 0x00)
pc = cpu.pc.get()
- cycle_test(cpu, 0xD9, 4+1)
- assert_default_registers(cpu, pc=pc+value)
+ cycle_test(cpu, 0xD9, 4+2)
+ assert_default_registers(cpu, pc=value+1, sp=2)
+
+def test_0xD9_handleInterrupt():
+ py.test.skip("figuring out how to do it")
-# ld_PC_HL
+# ld_PC_HL
def test_0xE9():
cpu = get_cpu()
value = 0x1234
@@ -1187,7 +1282,6 @@
assert_default_registers(cpu, f=~flags[i] & 0xFF, pc=pc+2)
value += 3
opCode += 0x08
-
# ldh_Ci_A
def test_0xE2():
@@ -1210,9 +1304,6 @@
cycle_test(cpu, 0xF2, 2)
assert_default_registers(cpu, a=valueA, bc=valueC)
-
-
-
# jp_nnnn
def test_0xC3():
cpu = get_cpu()
@@ -1230,12 +1321,26 @@
# ei
def test_0xFB():
- py.test.skip("interupt error")
+ py.test.skip("cycle bug in cpu")
cpu = get_cpu()
+ cpu.sp.set(0)
cpu.ime = False
+ cpu.halted = False
prepare_for_fetch(cpu, 0x00)
cycle_test(cpu, 0xFB, 1+1)
assert cpu.ime == True
+
+ cpu.reset()
+ cpu.sp.set(0)
+ cpu.ime = True
+ cpu.halted = False
+ cpu.interrupt.vBlank.setPending()
+ cpu.interrupt.setInterruptEnable(True)
+ assert cpu.interrupt.isPending() == True
+ prepare_for_fetch(cpu, 0x00)
+ cycle_test(cpu, 0xFB, 1+1+4)
+ assert cpu.interrupt.isPending() == False
+ assert cpu.ime == True
# call_NZ_nnnn
def test_0xC4():
@@ -1303,6 +1408,7 @@
# rst(0x00) to rst(0x38)
def test_0xC7_to_0xFF():
+ py.test.skip("cycle bug in cpu")
cpu = get_cpu()
opCode = 0xC7
rstValue = 0x00
Added: pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_register.py
==============================================================================
--- (empty file)
+++ pypy/branch/gameboy-emulator/pypy/lang/gameboy/test/test_register.py Tue Apr 8 00:46:33 2008
@@ -0,0 +1,158 @@
+from pypy.lang.gameboy.cpu import *
+from pypy.lang.gameboy.ram import *
+from pypy.lang.gameboy import *
+from pypy.lang.gameboy.interrupt import *
+
+class Memory(object):
+ def __init__(self):
+ self.memory = [0xFF]*0xFFFFF
+
+ def write(self, address, data):
+ self.memory[address] = data
+
+ def read(self, address):
+ return self.memory[address]
+
+global TEST_CPU
+
+TEST_CPU = None
+def get_cpu(new=False):
+ if new:
+ cpu = CPU(Interrupt(), Memory())
+ cpu.setROM([0]*0xFFFF);
+ return cpu
+ global TEST_CPU
+ if TEST_CPU == None:
+ TEST_CPU = get_cpu(True)
+ TEST_CPU.reset()
+ return TEST_CPU
+
+# ------------------------------------------------------------
+# TEST REGISTER
+def test_register_constructor():
+ register = Register(get_cpu())
+ assert register.get() == 0
+ value = 10
+ register = Register(get_cpu(), value)
+ assert register.get() == value
+
+def test_register():
+ register = Register(get_cpu())
+ value = 2
+ oldCycles = register.cpu.cycles
+ register.set(value)
+ assert register.get() == value
+ assert oldCycles-register.cpu.cycles == 1
+
+def test_register_bounds():
+ register = Register(get_cpu())
+ value = 0x1234FF
+ register.set(value)
+ assert register.get() == 0xFF
+
+def test_reset():
+ value = 0x12
+ register = Register(get_cpu(), value)
+ register.set(value+1)
+ assert register.get() == value+1
+ register.reset()
+ assert register.get() == value
+
+# ------------------------------------------------------------
+# TEST DOUBLE REGISTER
+
+def test_double_register_constructor():
+ cpu = get_cpu()
+ register = DoubleRegister(cpu)
+ assert register.get() == 0
+ assert register.getHi() == 0
+ assert register.getLo() == 0
+ value = 0x1234
+ reg1 = Register(cpu)
+ reg1.set(0x12)
+ reg2 = Register(cpu)
+ reg2.set(0x34)
+ register = DoubleRegister(cpu, reg1, reg2)
+ assert register.hi == reg1
+ assert register.lo == reg2
+ assert register.getHi() == reg1.get()
+ assert register.getLo() == reg2.get()
+
+def test_double_register():
+ register = DoubleRegister(get_cpu())
+ value = 0x1234
+ oldCycles = register.cpu.cycles
+ register.set(value)
+ assert oldCycles-register.cpu.cycles == 1
+ assert register.get() == value
+
+def test_double_register_bounds():
+ register = DoubleRegister(get_cpu())
+ value = 0xFFFF1234
+ register.set(value)
+ assert register.get() == 0x1234
+
+def test_double_register_hilo():
+ register = DoubleRegister(get_cpu())
+ value = 0x1234
+ valueHi = 0x12
+ valueLo = 0x34
+ oldCycles = register.cpu.cycles
+ register.set(valueHi, valueLo)
+ assert oldCycles-register.cpu.cycles == 2
+ assert register.getHi() == valueHi
+ assert register.getLo() == valueLo
+ assert register.get() == value
+
+ valueHi = 0x56
+ oldCycles = register.cpu.cycles
+ register.setHi(valueHi)
+ assert oldCycles-register.cpu.cycles == 1
+ assert register.getHi() == valueHi
+ assert register.getLo() == valueLo
+
+ valueLo = 0x78
+ oldCycles = register.cpu.cycles
+ register.setLo(valueLo)
+ assert oldCycles-register.cpu.cycles == 1
+ assert register.getHi() == valueHi
+ assert register.getLo() == valueLo
+
+
+def test_double_register_methods():
+ print("test_double_register_methods")
+ value = 0x1234
+ register = DoubleRegister(get_cpu())
+ register.set(value)
+
+ oldCycles = register.cpu.cycles
+ register.inc(False)
+ assert oldCycles-register.cpu.cycles == 0
+ assert register.get() == value+1
+
+ register.set(value)
+ oldCycles = register.cpu.cycles
+ register.inc(True)
+ assert oldCycles-register.cpu.cycles == 2
+ assert register.get() == value+1
+
+ oldCycles = register.cpu.cycles
+ register.dec()
+ assert oldCycles-register.cpu.cycles == 2
+ assert register.get() == value
+
+ addValue = 0x1001
+ oldCycles = register.cpu.cycles
+ register.add(addValue)
+ assert oldCycles-register.cpu.cycles == 3
+ assert register.get() == value+addValue
+
+
+def test_double_register_reset():
+ value = 0x1234;
+
+ register = DoubleRegister(get_cpu(), value)
+ register.set(value+1)
+ assert register.get() == value+1;
+ register.reset()
+ assert register.get() == value
\ No newline at end of file
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