[pypy-svn] r55706 - in pypy/dist/pypy/lang/gameboy: . test

cami at codespeak.net cami at codespeak.net
Mon Jun 9 20:08:49 CEST 2008


Author: cami
Date: Mon Jun  9 20:08:49 2008
New Revision: 55706

Modified:
   pypy/dist/pypy/lang/gameboy/cpu.py
   pypy/dist/pypy/lang/gameboy/gameboy_implementation.py
   pypy/dist/pypy/lang/gameboy/test/test_cpu.py
   pypy/dist/pypy/lang/gameboy/test/test_cpu_2.py
Log:
added debug logger
added explicit load test to control the opcodes


Modified: pypy/dist/pypy/lang/gameboy/cpu.py
==============================================================================
--- pypy/dist/pypy/lang/gameboy/cpu.py	(original)
+++ pypy/dist/pypy/lang/gameboy/cpu.py	Mon Jun  9 20:08:49 2008
@@ -2,6 +2,7 @@
 from pypy.lang.gameboy import constants
 from pypy.lang.gameboy.ram import *
 from pypy.lang.gameboy.interrupt import *
+from pypy.lang.gameboy.debug import *
 
 # ---------------------------------------------------------------------------
 
@@ -356,14 +357,17 @@
 
     def handle_pending_interrupts(self):
         if self.halted:
-            if self.interrupt.is_pending():
-                self.halted = False
-                self.cycles -= 4
-            elif (self.cycles > 0):
-                self.cycles = 0
+            self.update_interrupt_cycles()
         if self.ime and self.interrupt.is_pending():
             self.lower_pending_interrupt()
             
+    def update_interrupt_cycles(self):
+        if self.interrupt.is_pending():
+            self.halted = False
+            self.cycles -= 4
+        elif (self.cycles > 0):
+            self.cycles = 0
+        
     def lower_pending_interrupt(self):
         for flag in self.interrupt.interrupt_flags:
             if flag.is_pending():
@@ -377,11 +381,13 @@
         #print "    fetch exe:", hex(opCode), "  "
         #, FETCH_EXECUTE_OP_CODES[opCode].__name__
         self.last_fetch_execute_op_code = opCode
+        if DEBUG: log(opCode, is_fetch_execute=True)
         FETCH_EXECUTE_OP_CODES[opCode](self)
         
         
     def execute(self, opCode):
         self.instruction_counter += 1
+        if DEBUG: log(opCode)
         #print self.instruction_counter, "-"*60
         #print "exe: ", hex(opCode),  "   "
         #, OP_CODES[opCode].__name__
@@ -1069,7 +1075,7 @@
 
 # OPCODE TABLES ---------------------------------------------------------------
 # Table with one to one mapping of simple OP Codes                
-FIRST_or_aDER_OP_CODES = [
+FIRST_ORDER_OP_CODES = [
     (0x00, CPU.nop),
     (0x08, CPU.load_mem_sp),
     (0x10, CPU.stop),
@@ -1109,14 +1115,14 @@
     (0xF8, CPU.store_fetch_added_sp_in_hl),
     (0xCB, CPU.fetch_execute),
     (0xCD, CPU.unconditional_call),
-    (0xC6, lambda s: CPU.add_a(s,               CPUFetchCaller(s))),
+    (0xC6, lambda s: CPU.add_a(s,                 CPUFetchCaller(s))),
     (0xCE, lambda s: CPU.add_a_with_carry(s,      CPUFetchCaller(s))),
     (0xD6, CPU.fetch_subtract_a),
     (0xDE, lambda s: CPU.subtract_with_carry_a(s, CPUFetchCaller(s))),
     (0xE6, lambda s: CPU.and_a(s,                 CPUFetchCaller(s))),
     (0xEE, lambda s: CPU.xor_a(s,                 CPUFetchCaller(s))),
     (0xF6, lambda s: CPU.or_a(s,                  CPUFetchCaller(s))),
-    (0xFE, lambda s: CPU.compare_a(s,           CPUFetchCaller(s))),
+    (0xFE, lambda s: CPU.compare_a(s,             CPUFetchCaller(s))),
     (0xC7, lambda s: CPU.restart(s, 0x00)),
     (0xCF, lambda s: CPU.restart(s, 0x08)),
     (0xD7, lambda s: CPU.restart(s, 0x10)),
@@ -1144,9 +1150,9 @@
 ]    
         
 
-REGISTER_SET_A    = [CPU.get_bc,    CPU.get_de, CPU.get_hl,   CPU.get_sp]
-REGISTER_SET_B    = [CPU.get_bc,    CPU.get_de, CPU.get_hl,   CPU.get_af]
-FLAG_REGISTER_SET = [CPU.is_not_z,  CPU.is_z,   CPU.is_not_c, CPU.is_c]
+REGISTER_SET_A    = [CPU.get_bc,   CPU.get_de, CPU.get_hl,   CPU.get_sp]
+REGISTER_SET_B    = [CPU.get_bc,   CPU.get_de, CPU.get_hl,   CPU.get_af]
+FLAG_REGISTER_SET = [CPU.is_not_z, CPU.is_z,   CPU.is_not_c, CPU.is_c]
 
 # Table for Register OP Codes: (startAddress, delta, method, regsiters)
 REGISTER_OP_CODES = [ 
@@ -1162,7 +1168,7 @@
     (0xC5, 0x10, CPU.push_double_register,      REGISTER_SET_B)
 ]
 # Table for Second Order OPCodes: (startAddress, delta, method, [args])
-SECOND_or_aDER_REGISTER_GROUP_OP_CODES = [
+SECOND_ORDER_REGISTER_GROUP_OP_CODES = [
     (0x00, 0x01, CPU.rotate_left_circular),    
     (0x08, 0x01, CPU.rotate_right_circular),    
     (0x10, 0x01, CPU.rotate_left),    
@@ -1178,11 +1184,12 @@
 
 # RAW OPCODE TABLE INITIALIZATION ----------------------------------------------
 
-FIRST_or_aDER_OP_CODES += create_register_op_codes(REGISTER_OP_CODES)
-FIRST_or_aDER_OP_CODES += create_group_op_codes(REGISTER_GROUP_OP_CODES)
-FIRST_or_aDER_OP_CODES += create_load_group_op_codes()
-SECOND_or_aDER_OP_CODES = create_group_op_codes(SECOND_or_aDER_REGISTER_GROUP_OP_CODES)
+FIRST_ORDER_OP_CODES  += create_register_op_codes(REGISTER_OP_CODES)
+FIRST_ORDER_OP_CODES  += create_group_op_codes(REGISTER_GROUP_OP_CODES)
+FIRST_ORDER_OP_CODES  += create_load_group_op_codes()
+SECOND_ORDER_OP_CODES  = create_group_op_codes(SECOND_ORDER_REGISTER_GROUP_OP_CODES)
+
 
+OP_CODES               = initialize_op_code_table(FIRST_ORDER_OP_CODES)
+FETCH_EXECUTE_OP_CODES = initialize_op_code_table(SECOND_ORDER_OP_CODES)
 
-OP_CODES = initialize_op_code_table(FIRST_or_aDER_OP_CODES)
-FETCH_EXECUTE_OP_CODES = initialize_op_code_table(SECOND_or_aDER_OP_CODES)

Modified: pypy/dist/pypy/lang/gameboy/gameboy_implementation.py
==============================================================================
--- pypy/dist/pypy/lang/gameboy/gameboy_implementation.py	(original)
+++ pypy/dist/pypy/lang/gameboy/gameboy_implementation.py	Mon Jun  9 20:08:49 2008
@@ -6,6 +6,7 @@
 from pypy.lang.gameboy.sound import SoundDriver
 from pypy.lang.gameboy.timer import Clock
 from pypy.lang.gameboy import constants
+from pypy.lang.gameboy import debug
 
 from pypy.rlib.rsdl import RSDL, RSDL_helper
 from pypy.rpython.lltypesystem import lltype, rffi
@@ -40,6 +41,7 @@
         finally:
             lltype.free(self.event, flavor='raw')
             RSDL.Quit()
+            debug.print_results()
         return 0
     
     def handle_events(self):
@@ -91,7 +93,8 @@
                 #if y%2 == 0 or True:
                 #    px = self.get_pixel_color(x, y)
                 #    str += ["#", "%", "+", " ", " "][px]
-                RSDL_helper.set_pixel(self.screen, x, y, self.pixel_map(x, y))
+                #RSDL_helper.set_pixel(self.screen, x, y, self.pixel_map(x, y))
+                pass
         #print str;
              
     def pixel_map(self, x, y):

Modified: pypy/dist/pypy/lang/gameboy/test/test_cpu.py
==============================================================================
--- pypy/dist/pypy/lang/gameboy/test/test_cpu.py	(original)
+++ pypy/dist/pypy/lang/gameboy/test/test_cpu.py	Mon Jun  9 20:08:49 2008
@@ -477,7 +477,7 @@
         set_registers(registers, 0)
         registers[i].set(value)
         cycle_test(cpu, opCode, 2);
-        assert  registers[i].get() == value +1
+        assert  registers[i].get() == value + 1
         cpu.reset()
         opCode += 0x10
         value += 3
@@ -492,7 +492,7 @@
         set_registers(registers, 0)
         registers[i].set(value)
         cycle_test(cpu, opCode, 2);
-        assert  registers[i].get() == value-1
+        assert  registers[i].get() == value - 1
         cpu.reset()
         cpu.reset()
         opCode += 0x10
@@ -612,10 +612,11 @@
         prepare_for_fetch(cpu, value)
         cycle_test(cpu, opCode, 2)
         assert registers[i].get()   == value
+        # one fetch
         assert cpu.pc.get() - oldPC == 1
         cpu.reset()
         opCode += 0x08
-        value += 3
+        value  += 3
         
 # ld_HLi_nn
 def test_0x36():
@@ -782,8 +783,8 @@
         if register == cpu.a:
             assert cpu.a.get() == 2*value
         else:
-            assert cpu.a.get() == valueA+value
-        value += 3
+            assert cpu.a.get() == valueA + value
+        value  += 3
         opCode += 0x01
 
 # adc_A_B to adx_A_A
@@ -869,7 +870,7 @@
         opCode += 0x01
     
 # and_A_B to and_A_A
-def test_0xA0_to_0xA7():
+def test_0xA0_to_0xA7_and_a():
     cpu       = get_cpu()
     opCode    = 0xA0
     value     = 0x12
@@ -956,7 +957,7 @@
         opCode += 0x01
 
 # ret_NZ to ret_C
-def test_0xC0():
+def test_0xC0_to_0xD8_return_on_condition():
     cpu    = get_cpu()
     flags  = [~constants.Z_FLAG, constants.Z_FLAG, ~constants.C_FLAG, constants.C_FLAG]
     opCode = 0xC0
@@ -1010,7 +1011,7 @@
     assert cpu.a.get() == value
 
 # ld_A_mem
-def test_0xFA():
+def test_0xFA_store_fetched_memory_in_a():
     cpu    = get_cpu()
     value  = 0x11
     valueA = 0x12
@@ -1119,18 +1120,20 @@
     assert cpu.pop() == 0x12
 
 # ld_PC_HL 
-def test_0xE9():
+def test_0xE9_store_hl_in_pc():
     cpu   = get_cpu()
     value = 0x1234
     cpu.hl.set(value)
+    cpu.pc.set(0)
     cycle_test(cpu, 0xE9, 1)
     assert_default_registers(cpu, pc=value, hl=value)
 
 # ld_SP_HL
-def test_0xF9():
+def test_0xF9_store_hl_in_sp():
     cpu   = get_cpu()
     value = 0x1234
     cpu.hl.set(value)
+    cpu.sp.set(0)
     cycle_test(cpu, 0xF9, 2)
     assert_default_registers(cpu, sp=value, hl=value)
 
@@ -1361,7 +1364,7 @@
     assert cpu.f.z_flag == True
 
 # rst(0x00) to rst(0x38)
-def test_0xC7_to_0xFF():
+def test_0xC7_to_0xFF_reset():
     cpu      = get_cpu()
     opCode   = 0xC7
     rstValue = 0x00
@@ -1369,10 +1372,10 @@
         cpu.reset()
         cpu.pc.set(0x1234)
         cycle_test(cpu, opCode, 4)
-        assert cpu.pop() == 0x34
+        assert cpu.pop()    == 0x34
         assert cpu.pop()    == 0x12
         assert cpu.pc.get() == rstValue
-        opCode += 0x08
+        opCode   += 0x08
         rstValue += 0x08
 
 # switching to other opcode set
@@ -1472,6 +1475,9 @@
             if register == cpu.hli:
                 cycles = 4
             cpu.reset()
+            if registerOpCode ==0xFF:
+                print "6544444444444444"
+                
             register.set(0)
             fetch_execute_cycle_test_second_order(cpu, registerOpCode, cycles)
             assert (register.get() & (1<<i)) >> i == 1
@@ -1506,6 +1512,127 @@
         opCode += 1
     
 
+# LOAD TEST -----------------------------------------------------------------
+# just for double checking ;)
 
+def load_test(cpu, test_set):
+    value = 0
+    for test in test_set:
+        opCode    = test[0]
+        reg_write = test[1]
+        reg_read  = test[2]
+        value = 1 + (value + 1) & 0xFE
+        reg_write.set(0)
+        reg_read.set(value)
+        cpu.execute(opCode)
+        assert reg_write.get() == reg_read.get(), hex(opCode)+" load failed!"
+        
+        
+def test_load_b():
+    cpu           = get_cpu()
+    read_register = cpu.b
+    load_test(cpu, 
+              [(0x40, read_register, cpu.b),
+               (0x41, read_register, cpu.c),
+               (0x42, read_register, cpu.d),
+               (0x43, read_register, cpu.e),
+               (0x44, read_register, cpu.h),
+               (0x45, read_register, cpu.l),
+               #(0x46, read_register, cpu.hli),
+               (0x47, read_register, cpu.a)])
+    
+def test_load_c():
+    cpu           = get_cpu()
+    read_register = cpu.c
+    load_test(cpu, 
+              [(0x48, read_register, cpu.b),
+               (0x49, read_register, cpu.c),
+               (0x4A, read_register, cpu.d),
+               (0x4B, read_register, cpu.e),
+               (0x4C, read_register, cpu.h),
+               (0x4D, read_register, cpu.l),
+               #(0x4E, read_register, cpu.hli),
+               (0x4F, read_register, cpu.a)])
+    
+    
+def test_load_d():
+    cpu           = get_cpu()
+    read_register = cpu.d
+    load_test(cpu, 
+              [(0x50, read_register, cpu.b),
+               (0x51, read_register, cpu.c),
+               (0x52, read_register, cpu.d),
+               (0x53, read_register, cpu.e),
+               (0x54, read_register, cpu.h),
+               (0x55, read_register, cpu.l),
+              # (0x56, read_register, cpu.hli),
+               (0x57, read_register, cpu.a)])
+    
+def test_load_e():
+    cpu           = get_cpu()
+    read_register = cpu.e
+    load_test(cpu, 
+              [(0x58, read_register, cpu.b),
+               (0x59, read_register, cpu.c),
+               (0x5A, read_register, cpu.d),
+               (0x5B, read_register, cpu.e),
+               (0x5C, read_register, cpu.h),
+               (0x5D, read_register, cpu.l),
+               #(0x5E, read_register, cpu.hli),
+               (0x5F, read_register, cpu.a)])
+    
+def test_load_h():
+    cpu           = get_cpu()
+    read_register = cpu.h
+    load_test(cpu, 
+              [(0x60, read_register, cpu.b),
+               (0x61, read_register, cpu.c),
+               (0x62, read_register, cpu.d),
+               (0x63, read_register, cpu.e),
+               (0x64, read_register, cpu.h),
+               (0x65, read_register, cpu.l),
+               #(0x66, read_register, cpu.hli),
+               (0x67, read_register, cpu.a)])
+    
+def test_load_l():
+    cpu           = get_cpu()
+    read_register = cpu.l
+    load_test(cpu, 
+              [(0x68, read_register, cpu.b),
+               (0x69, read_register, cpu.c),
+               (0x6A, read_register, cpu.d),
+               (0x6B, read_register, cpu.e),
+               (0x6C, read_register, cpu.h),
+               (0x6D, read_register, cpu.l),
+               #(0x6E, read_register, cpu.hli),
+               (0x6F, read_register, cpu.a)])
+    
+def test_load_hli():
+    cpu           = get_cpu()
+    read_register = cpu.hli
+    load_test(cpu, 
+              [(0x70, read_register, cpu.b),
+               (0x71, read_register, cpu.c),
+               (0x72, read_register, cpu.d),
+               (0x73, read_register, cpu.e),
+               (0x74, read_register, cpu.h),
+               (0x75, read_register, cpu.l),
+               (0x77, read_register, cpu.a)])
+    
+def test_load_a():
+    cpu           = get_cpu()
+    read_register = cpu.a
+    load_test(cpu, 
+              [(0x78, read_register, cpu.b),
+               (0x79, read_register, cpu.c),
+               (0x7A, read_register, cpu.d),
+               (0x7B, read_register, cpu.e),
+               (0x7C, read_register, cpu.h),
+               (0x7D, read_register, cpu.l),
+               #(0x7E, read_register, cpu.hli),
+               (0x7F, read_register, cpu.a)])
+    
+    
+    
 
     
\ No newline at end of file

Modified: pypy/dist/pypy/lang/gameboy/test/test_cpu_2.py
==============================================================================
--- pypy/dist/pypy/lang/gameboy/test/test_cpu_2.py	(original)
+++ pypy/dist/pypy/lang/gameboy/test/test_cpu_2.py	Mon Jun  9 20:08:49 2008
@@ -123,7 +123,7 @@
 # Tests -----------------------------------------------------------------------
 
 
-def test_add_a_with_carry():
+def test_pa_with_carry():
     cpu = get_cpu()
     cpu.f.set(0xFF)
     cpu.a.set(0x00)
@@ -238,6 +238,12 @@
     method_value_call(cpu, CPU.and_a, 0x12)
     assert cpu.a.get() == 0x12
     assert_flags(cpu, z=False, n=False, h=True, c=False)
+    
+    cpu.f.set(0x00)
+    cpu.a.set(0xFF)
+    method_value_call(cpu, CPU.and_a, 0x12)
+    assert cpu.a.get() == 0x12
+    assert_flags(cpu, z=False, n=False, h=True, c=False)
       
 def test_or_a():
     cpu = get_cpu()



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