[pypy-svn] r55192 - in pypy/dist/pypy/lang/gameboy: . test

cami at codespeak.net cami at codespeak.net
Sat May 24 16:17:16 CEST 2008


Author: cami
Date: Sat May 24 16:17:14 2008
New Revision: 55192

Modified:
   pypy/dist/pypy/lang/gameboy/cartridge.py
   pypy/dist/pypy/lang/gameboy/test/test_memory_bank_controller.py
Log:
added more memory bank controller tests


Modified: pypy/dist/pypy/lang/gameboy/cartridge.py
==============================================================================
--- pypy/dist/pypy/lang/gameboy/cartridge.py	(original)
+++ pypy/dist/pypy/lang/gameboy/cartridge.py	Sat May 24 16:17:14 2008
@@ -286,9 +286,12 @@
             return self.rom[address] & 0xFF
         elif address <= 0x7FFF:# 4000-7FFF
             return self.rom[self.rom_bank + (address & 0x3FFF)] & 0xFF
-        elif address >= 0xA000 and address <= 0xBFFF and self.ram_enable: # A000-BFFF
-            return self.ram[self.ram_bank + (address & 0x1FFF)] & 0xFF
-        raise Exception("MBC: Invalid address, out of range")
+        elif address >= 0xA000 and address <= 0xBFFF: # A000-BFFF
+            if self.ram_enable:
+                return self.ram[self.ram_bank + (address & 0x1FFF)] & 0xFF
+            else:
+                raise Exception("RAM is not Enabled")
+        raise Exception("MBC: Invalid address, out of range: %s" % hex(address))
     
     def write(self, address, data):
         raise Exception("MBC: Invalid write access")
@@ -346,7 +349,7 @@
         elif address >= 0xA000 and address <= 0xBFFF and self.ram_enable: # A000-BFFF
             self.ram[self.ram_bank + (address & 0x1FFF)] = data
         else:
-            raise Exception("Invalid memory Access")
+            raise Exception("Invalid memory Access address: %s" % hex(address))
 
     def write_ram_enable(self, address, data):
         if self.ram_size > 0:
@@ -390,10 +393,17 @@
                     min_rom_bank_size=2,   
                     max_rom_bank_size=16)
         
-
+    
     def read(self, address):
         if address > 0xA1FF:
-            return 0xFF
+            raise Exception("MBC2 out of Bounds: %s" % hex(address))
+        elif address >= 0xA000:
+            return self.ram[address & 0x01FF]
+        elif address >= 0xA000 and address <= 0xA1FF: # A000-BFFF
+            if self.ram_enable:
+                return self.ram[self.ram_bank + (address & 0x1FFF)] & 0xFF
+            else:
+                raise Exception("RAM is not Enabled")
         else:
             return MBC.read(self, address)
         
@@ -444,20 +454,20 @@
 
     def reset(self):
         MBC.reset(self)
-        self.clockLDaysclockLControl = None
+        self.clock_latched_daysclock_latched_control = None
         self.clock_time     = self.clock.get_time()
         self.clock_latch     = 0
         self.clock_register = 0
-        self.clockSeconds   = 0
-        self.clockMinutes   = 0
-        self.clockHours     = 0
-        self.clockDays      = 0
-        self.clockControl   = 0
-        self.clockLSeconds  = 0
-        self.clockLMinutes  = 0
-        self.clockLHours    = 0
-        self.clockLDays     = 0
-        self.clockLControl  = 0
+        self.clock_seconds   = 0
+        self.clock_minutes   = 0
+        self.clock_hours     = 0
+        self.clock_days      = 0
+        self.clock_control   = 0
+        self.clock_latched_seconds  = 0
+        self.clock_latched_minutes  = 0
+        self.clock_latched_hours    = 0
+        self.clock_latched_days     = 0
+        self.clock_latched_control  = 0
 
 
     def read(self, address):
@@ -471,15 +481,15 @@
         
     def read_clock_data(self, address):
         if self.clock_register == 0x08:
-            return self.clockLSeconds
+            return self.clock_latched_seconds
         if self.clock_register == 0x09:
-            return self.clockLMinutes
+            return self.clock_latched_minutes
         if self.clock_register == 0x0A:
-            return self.clockLHours
+            return self.clock_latched_hours
         if self.clock_register == 0x0B:
-            return self.clockLDays
+            return self.clock_latched_days
         if self.clock_register == 0x0C:
-            return self.clockLControl
+            return self.clock_latched_control
         raise Exception("MBC*.read_clock_data invalid address %i")
     
     def write(self, address, data):
@@ -522,52 +532,52 @@
         else:
             self.update_clock()
             if self.clock_register == 0x08:
-                self.clockSeconds = data
+                self.clock_seconds = data
             if self.clock_register == 0x09:
-                self.clockMinutes = data
+                self.clock_minutes = data
             if self.clock_register == 0x0A:
-                self.clockHours = data
+                self.clock_hours = data
             if self.clock_register == 0x0B:
-                self.clockDays = data
+                self.clock_days = data
             if self.clock_register == 0x0C:
-                self.clockControl = (self.clockControl & 0x80) | data
+                self.clock_control = (self.clock_control & 0x80) | data
         
 
     def latch_clock(self):
         self.update_clock()
-        self.clockLSeconds = self.clockSeconds
-        self.clockLMinutes = self.clockMinutes
-        self.clockLHours   = self.clockHours
-        self.clockLDays    = self.clockDays & 0xFF
-        self.clockLControl = (self.clockControl & 0xFE) | ((self.clockDays >> 8) & 0x01)
+        self.clock_latched_seconds = self.clock_seconds
+        self.clock_latched_minutes = self.clock_minutes
+        self.clock_latched_hours   = self.clock_hours
+        self.clock_latched_days    = self.clock_days & 0xFF
+        self.clock_latched_control = (self.clock_control & 0xFE) | ((self.clock_days >> 8) & 0x01)
 
 
     def update_clock(self):
         now = self.clock.get_time()
-        if (self.clockControl & 0x40) == 0:
+        if (self.clock_control & 0x40) == 0:
             elapsed = now - self.clock_time
             while elapsed >= 246060:
                 elapsed -= 246060
-                self.clockDays+=1
+                self.clock_days+=1
             while elapsed >= 6060:
                 elapsed -= 6060
-                self.clockHours+=1
+                self.clock_hours+=1
             while elapsed >= 60:
                 elapsed -= 60
-                self.clockMinutes+=1
-            self.clockSeconds += elapsed
-            while self.clockSeconds >= 60:
-                self.clockSeconds -= 60
-                self.clockMinutes+=1
-            while self.clockMinutes >= 60:
-                self.clockMinutes -= 60
-                self.clockHours+=1
-            while self.clockHours >= 24:
-                self.clockHours -= 24
-                self.clockDays+=1
-            while self.clockDays >= 512:
-                self.clockDays -= 512
-                self.clockControl |= 0x80
+                self.clock_minutes+=1
+            self.clock_seconds += elapsed
+            while self.clock_seconds >= 60:
+                self.clock_seconds -= 60
+                self.clock_minutes+=1
+            while self.clock_minutes >= 60:
+                self.clock_minutes -= 60
+                self.clock_hours+=1
+            while self.clock_hours >= 24:
+                self.clock_hours -= 24
+                self.clock_days+=1
+            while self.clock_days >= 512:
+                self.clock_days -= 512
+                self.clock_control |= 0x80
         self.clock_time = now
 
 

Modified: pypy/dist/pypy/lang/gameboy/test/test_memory_bank_controller.py
==============================================================================
--- pypy/dist/pypy/lang/gameboy/test/test_memory_bank_controller.py	(original)
+++ pypy/dist/pypy/lang/gameboy/test/test_memory_bank_controller.py	Sat May 24 16:17:14 2008
@@ -3,6 +3,7 @@
 from pypy.lang.gameboy.timer import Clock
 from pypy.lang.gameboy import constants
 import py
+import pdb
 
 def get_clock_driver():
     return Clock()
@@ -25,7 +26,7 @@
  
  
  
-def read_write_test(mbc, lower, upper):
+def basic_read_write_test(mbc, lower, upper):
     write_bounds_test(mbc, lower, upper)
     read_bounds_test(mbc, lower, upper)
     
@@ -52,15 +53,25 @@
         py.test.fail("lower bound check failed")
     except:
         pass
-    for address in range(lower, upper):
-       assert mbc.read(address) != None
+    for address in range(lower, upper, 1):
+        assert mbc.read(address) != None
     try:
         mbc.read(upper+1)
         py.test.fail("lower upper check failed")
     except:
         pass
     
+def write_ram_enable_test(mbc):
+    value = 0
+    for address in range(0x1FFF+1):
+        mbc.write(address, 0x0A)
+        assert mbc.ram_enable == True
+        mbc.write(address, 0x00)
+        assert mbc.ram_enable == False
+    
+
 # -----------------------------------------------------------------------------
+
 def test_mbc_init():
     try:
         MBC(get_ram(), get_rom(), get_clock_driver())
@@ -112,7 +123,7 @@
     except:
         pass
  
-def test_mbc_read_write_test(mbc=None):  
+def test_mbc_basic_read_write_test(mbc=None):  
     if mbc==None:
         mbc = MBC([0]*0xFFFF,[0]*0xFFFF, get_clock_driver(),1, 0xFFFF, 2, 0xFFFF)
 
@@ -155,7 +166,7 @@
 def get_mbc1(rom_size=128, ram_size=4):
     return MBC1(get_rom(rom_size), get_ram(ram_size), get_clock_driver())
 
-def test_mbc1_create():
+def test_mbc1():
     mbc1 = get_mbc1()
     assert mbc1.rom_bank == constants.ROM_BANK_SIZE
     assert mbc1.memory_model == 0
@@ -166,42 +177,60 @@
     fail_ini_test(get_mbc1, 1, 4)
     fail_ini_test(get_mbc1, 129, 4)
     
-def test_mbc1_read_write():
-    mbc = get_mbc1()
-    read_write_test(mbc, 0, 0x7FFF)
-    value = 0
-    for address in range(0x1FFF+1):
-        mbc.write(address, 0x0A)
-        assert mbc.ram_enable == True
-        mbc.write(address, 0x00)
-        assert mbc.ram_enable == False
+    basic_read_write_test(mbc1, 0, 0x7FFF)
     
-    import pdb
+def test_mbc1_write_ram_enable():
+    write_ram_enable_test(get_mbc1())
+        
+def test_mbc_write_rom_bank_test1():
+    mbc= get_mbc1()
     value = 1   
-    for address in range(0x2000, 0x3FFF):
+    for address in range(0x2000, 0x3FFF+1):
         mbc.memory_model = 0
         rom_bank = mbc.rom_bank
-        #pdb.runcall(mbc.write, address, value)
         mbc.write(address, value)
         assert mbc.rom_bank == ((rom_bank & 0x180000) + \
                                 ((value & 0x1F) << 14)) & mbc.rom_size
         mbc.memory_model = 10
         mbc.write(address, value)
         assert mbc.rom_bank == ((value & 0x1F) << 14) & mbc.rom_size
-        value = (value+1) % (0x1F-1) +1 
+        value = (value+1) % (0x1F-1) +1
         
+def test_mbc1_write_rom_bank_test2():
+    mbc = get_mbc1()        
+    value = 1   
+    for address in range(0x4000, 0x5FFF+1):
+        mbc.memory_model = 0
+        rom_bank = mbc.rom_bank
+        mbc.write(address, value)
+        assert mbc.rom_bank == ((mbc.rom_bank & 0x07FFFF) + \
+                                ((value & 0x03) << 19))  & mbc.rom_size;
+        mbc.memory_model = 10
+        mbc.write(address, value)
+        assert mbc.ram_bank == ((value & 0x03) << 13) & mbc.ram_size
+        value += 1
+        value %= 0xFF 
         
+def test_mbc1_read_memory_model():
+    mbc = get_mbc1()       
+    value = 1   
+    for address in range(0x6000, 0x7FFF+1):
+        mbc.write(address, value)
+        assert mbc.memory_model == (value & 0x01)
+        value += 1
+        value %= 0xFF
         
-def test_mbc1_write():  
-    py.test.skip("buggy implementation of MBC1++")
-    mbc1 = get_mbc1()
-    test_mbc_read_write_test(mbc1)
-    
-def test_mbc1_read():
-    py.test.skip("not yet implemented")
-    mbc1 = get_mbc1()
-    # the same as in mbc
-    pass
+def test_mbc1_read_write_ram():
+    mbc = get_mbc1()        
+    value = 1
+    mbc.ram_enable = True
+    for address in range(0xA000, 0xBFFF+1):
+        mbc.write(address, value)
+        #pdb.runcall(mbc.write, address, value)
+        assert mbc.ram[mbc.ram_bank + (address & 0x1FFF)] == value
+        assert mbc.read(address) == value;
+        value += 1
+        value %= 0xFF 
 
 # -----------------------------------------------------------------------------
 
@@ -209,41 +238,160 @@
     return MBC2(get_rom(rom_size), get_ram(ram_size), get_clock_driver())
 
 def test_mbc2_create():
-    get_mbc2()
-    fail_ini_test(get_mbc2, 2, 0)
-    fail_ini_test(get_mbc2, 2, 2)
-    fail_ini_test(get_mbc2, 1, 1)
-    fail_ini_test(get_mbc2, 17, 1)
-    
-    
-def test_mbc2_read_write():
-    py.test.skip("not yet implemented")
     mbc2 = get_mbc2()
+    fail_ini_test(mbc2, 2, 0)
+    fail_ini_test(mbc2, 2, 2)
+    fail_ini_test(mbc2, 1, 1)
+    fail_ini_test(mbc2, 17, 1)
+    # only to the upper border of mbc
+    basic_read_write_test(mbc2, 0, 0x7FFF)
     
-
-def test_mbc2_write():
-    py.test.skip("not yet implemented")
-    mbc2 = get_mbc2()
+    
+def test_mbc2_write_ram_enable():
+    mbc = get_mbc2()
+    value = 0
+    for address in range(0x1FFF+1):
+        mbc.ram_enable = -1
+        mbc.write(address, 0x0A)
+        if (address & 0x0100) == 0: 
+            assert mbc.ram_enable == True
+            mbc.write(address, 0x00)
+            assert mbc.ram_enable == False
+        else:
+            assert mbc.ram_enable == -1
+        
+def test_mbc2_write_rom_bank_test1():
+    mbc = get_mbc2()
+    value = 1   
+    for address in range(0x2000, 0x3FFF+1):
+        mbc.rom_bank = -1
+        mbc.write(address, value)
+        if (address & 0x0100) != 0:
+            assert mbc.rom_bank == ((value & 0x0F) << 14) & mbc.rom_size
+        else:
+            assert mbc.rom_bank == -1
+        value = (value + 1) % (0x0F-1) + 1 
+        
+def test_mbc2_read_write_ram():
+    mbc = get_mbc2()        
+    value = 1
+    mbc.ram_enable = True
+    for address in range(0xA000, 0xA1FF+1):
+        mbc.write(address, value)
+        assert mbc.ram[(address & 0x01FF)] == value & 0x0F
+        assert mbc.read(address) == value;
+        value += 1
+        value %= 0x0F 
     
 # -----------------------------------------------------------------------------
-
+    
 def get_mbc3(rom_size=128, ram_size=4):
     return MBC3(get_rom(rom_size), get_ram(ram_size), get_clock_driver())
 
 def test_mbc3_create():
-    get_mbc3()
-    fail_ini_test(get_mbc3, 128, -1)
-    fail_ini_test(get_mbc3, 128, 5)
-    fail_ini_test(get_mbc3, 1, 4)
-    fail_ini_test(get_mbc3, 129, 4)
-    
-def test_mbc3_read():
-    py.test.skip("not yet implemented")
     mbc3 = get_mbc3()
+    fail_ini_test(mbc3, 128, -1)
+    fail_ini_test(mbc3, 128, 5)
+    fail_ini_test(mbc3, 1, 4)
+    fail_ini_test(mbc3, 129, 4)
+    basic_read_write_test(mbc3, 0, 0x7FFF)
+    
+def test_mbc3_write_ram_enable():
+    write_ram_enable_test(get_mbc3())
+        
+def test_mbc3_write_rom_bank():
+    mbc= get_mbc3()
+    value = 1   
+    for address in range(0x2000, 0x3FFF+1):
+        mbc.memory_model = 0
+        rom_bank = mbc.rom_bank
+        mbc.write(address, value)
+        if value == 0:
+            assert mbc.rom_bank == ((1 & 0x7F) << 14) & mbc.rom_size
+        else:
+            assert mbc.rom_bank == ((value & 0x7F) << 14) & mbc.rom_size
+        value += 1
+        value %= 0xFF
+        
+def test_mbc3_write_ram_bank():
+    mbc = get_mbc3()        
+    value = 1   
+    for address in range(0x4000, 0x5FFF+1):
+        mbc.memory_model = 0
+        mbc.write(address, value)
+        if value >= 0 and value <= 0x03:
+            assert mbc.ram_bank == (value << 13) & mbc.ram_size
+        else:
+           assert mbc.ram_bank == -1;
+           assert mbc.clock_register == value
+        value += 1
+        value %= 0xFF 
+        
+def test_mbc3_write_clock_latch():
+    mbc = get_mbc3()       
+    value = 1   
+    for address in range(0x6000, 0x7FFF+1):
+        mbc.write(address, value)
+        if value == 0 or value == 1:    
+            assert mbc.clock_latch == value
+        if value == 1:
+            # clock update check...
+            pass
+        value += 1
+        value %= 0xFF
+        
+def test_mbc3_read_write_ram():
+    mbc = get_mbc3()        
+    value = 1
+    mbc.ram_enable = True
+    for address in range(0xA000, 0xBFFF+1):
+        mbc.write(address, value)
+        #pdb.runcall(mbc.write, address, value)
+        assert mbc.ram[mbc.ram_bank + (address & 0x1FFF)] == value
+        assert mbc.read(address) == value;
+        value += 1
+        value %= 0xFF
+        
+def test_mbc3_read_write_clock():
+    mbc = get_mbc3()        
+    value = 1
+    mbc.ram_enable = True
+    mbc.ram_bank = -1
+    old_clock_value = -2
+    for address in range(0xA000, 0xBFFF+1):
+        mbc.clock_register = 0x08
+        mbc.write(address, value)
+        assert mbc.clock_seconds == value
+        
+        mbc.clock_register = 0x09
+        mbc.write(address, value)
+        assert mbc.clock_minutes == value
+        
+        mbc.clock_register = 0x0A
+        mbc.write(address, value)
+        assert mbc.clock_hours == value
+        
+        mbc.clock_register = 0x0B
+        mbc.write(address, value)
+        assert mbc.clock_days == value
+        
+        mbc.clock_register = 0x0C
+        clock_control = mbc.clock_control
+        mbc.write(address, value)
+        assert mbc.clock_control == ((clock_control & 0x80) | value)
+        
+        value += 1
+        value %= 0xFF
 
-def test_mbc3_write():
+def test_mbc3_update_clock():
     py.test.skip("not yet implemented")
-    mbc3 = get_mbc3()
+    mbc = get_mbc3()
+    
+    
+def test_mbc3_latch_clock():
+    py.test.skip("not yet implemented")
+    mbc = get_mbc3()
+    
     
 # -----------------------------------------------------------------------------
 



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