[pypy-svn] r58461 - in pypy/branch/oo-jit/pypy/jit/codegen/x86_64: . test
witulski at codespeak.net
witulski at codespeak.net
Sun Sep 28 23:58:29 CEST 2008
Author: witulski
Date: Sun Sep 28 23:58:28 2008
New Revision: 58461
Modified:
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_rgenop.py
pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_simple.py
Log:
Added IDIV + Test
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/assembler.py Sun Sep 28 23:58:28 2008
@@ -29,7 +29,7 @@
# This method wirtes the bitencodings into
# the memory. The parameters are overwritten
-# if one of the operands is an register
+# if one of the operands is an register.
# tttn isn't used yet
# extra is an extra byte for long opcodes like IMUL
def make_two_operand_instr(W = None, R = None, X = None, B = None, opcode =None, m = None, md1 = None, md2 = None, tttn = None, extra = None):
@@ -78,7 +78,7 @@
# This method wirtes the bitencodings into
# the memory. The parameters are overwritten
-# if one of the operands is an register
+# if one of the operands is an register.
# tttn codes the flags and is only used by SETcc
def make_one_operand_instr(W = None, R = None, X = None, B = None, opcode = None, m = None, md1 = None, md2 = None, tttn=None, extra = None):
def quadreg_instr(self, arg1):
@@ -240,6 +240,19 @@
def DEC(self, op1):
method = getattr(self, "_DEC"+op1.to_string())
method(op1)
+
+ def IDIV(self, op1):
+ method = getattr(self, "_IDIV"+op1.to_string())
+ method(op1)
+
+ def IMUL(self, op1, op2):
+ method = getattr(self, "_IMUL"+op1.to_string()+op2.to_string())
+ # exchange the two arguments because
+ # the result is in the first register
+ if(op1.to_string()=="_QWREG" and op2.to_string()=="_QWREG"):
+ method(op2, op1)
+ else:
+ method(op1, op2)
def INC(self, op1):
method = getattr(self, "_INC"+op1.to_string())
@@ -276,20 +289,6 @@
def MOV(self, op1, op2):
method = getattr(self, "_MOV"+op1.to_string()+op2.to_string())
method(op1, op2)
-
-
- def IDIV(self, op1):
- method = getattr(self, "_IDIV"+op1.to_string())
- method(op1)
-
- def IMUL(self, op1, op2):
- method = getattr(self, "_IMUL"+op1.to_string()+op2.to_string())
- # exchange the two arguments because
- # the result is in the first register
- if(op1.to_string()=="_QWREG" and op2.to_string()=="_QWREG"):
- method(op2, op1)
- else:
- method(op1, op2)
def NEG(self, op1):
method = getattr(self, "_NEG"+op1.to_string())
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/rgenop.py Sun Sep 28 23:58:28 2008
@@ -129,9 +129,11 @@
# FIXME: supports only RAX with QWREG
def op_int_div(self, gv_x, gv_y):
gv_z = self.allocate_register("rax")
+ gv_w = self.allocate_register("rdx")
self.mc.MOV(gv_z, gv_x)
+ self.mc.XOR(gv_w, gv_w)
self.mc.IDIV(gv_y)
- return gv_y #FIXME: return gv_x?
+ return gv_z #FIXME: return gv_x?
#FIXME: can only jump 32bit
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_rgenop.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_rgenop.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_rgenop.py Sun Sep 28 23:58:28 2008
@@ -200,13 +200,17 @@
res = fnptr(12345,-9876)
assert res == -121919220
- #Floating point exception
- #def test_idiv(self):
- # rgenop = self.RGenOp()
- # div_function = make_div(rgenop)
- # fnptr = self.cast(div_function,2)
- # res = fnptr(100,2)
- # assert res == 50
+ #BUG ignores rdx
+ def test_idiv(self):
+ rgenop = self.RGenOp()
+ div_function = make_div(rgenop)
+ fnptr = self.cast(div_function,2)
+ res = fnptr(100,2)
+ assert res == 50
+ res = fnptr(168,4)
+ assert res == 42
+ res = fnptr(72057594037927935,5)
+ assert res == 14411518807585587
def test_greater(self):
rgenop = self.RGenOp()
@@ -282,8 +286,8 @@
rgenop = self.RGenOp()
cmp_function = make_cmp(rgenop, "int_eq",42)
fnptr = self.cast(cmp_function,1)
- # res = fnptr(42)
- # assert res == 1
+ res = fnptr(42)
+ assert res == 1
res = fnptr(23)
assert res == 0
cmp_function = make_cmp(rgenop, "int_eq")
@@ -306,7 +310,7 @@
assert res == 0
res = fnptr(244,756)
assert res == 0
- res = fnptr(-1,9223372036854775807)
+ res = fnptr(-1,9223372036854775807) #FFFF.... != 7FFF...
assert res == 0
def test_not_equal(self):
Modified: pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_simple.py
==============================================================================
--- pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_simple.py (original)
+++ pypy/branch/oo-jit/pypy/jit/codegen/x86_64/test/test_simple.py Sun Sep 28 23:58:28 2008
@@ -30,11 +30,10 @@
builder.finish_and_return(token, genv_result)
num = fp(1280, 20)
assert num == 1300
- num = fp(1280, -80)
- assert num == 1200
num = fp(1280, 1000)
assert num == 2280
- print num
+ num = fp(1280, -80)
+ assert num == 1200
def test_add_twice(self):
builder, fp, inputargs_gv, token = make_testbuilder(2)
More information about the Pypy-commit
mailing list