[pypy-svn] r80028 - pypy/branch/arm-backend/pypy/jit/backend/arm

[david at codespeak.net]

Author: david
Date: Mon Dec 13 11:56:20 2010
New Revision: 80028

Modified:
   pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py
Log:
Fix calls with parameters on the stack and guard_exception

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py	Mon Dec 13 11:56:20 2010
@@ -243,7 +243,6 @@
         adr = args[0]
         cond =  self._emit_call(adr, op.getarglist()[1:], regalloc, fcond,
                                 op.result, spill_all_regs=spill_all_regs)
-
         descr = op.getdescr()
         #XXX Hack, Hack, Hack
         if op.result and not we_are_translated() and not isinstance(descr, LoopToken):
@@ -282,9 +281,8 @@
             n = stack_args*WORD
             self._adjust_sp(n, fcond=fcond)
             for i in range(4, n_args):
-                reg, box = regalloc._ensure_value_is_boxed(args[i], regalloc)
-                self.mc.STR_ri(reg.value, r.sp.value, (i-4)*WORD)
-                regalloc.possibly_free_var(box)
+                self.regalloc_mov(regalloc.loc(args[i]), r.ip)
+                self.mc.STR_ri(r.ip.value, r.sp.value, (i-4)*WORD)
 
         #the actual call
         self.mc.BL(adr)
@@ -329,14 +327,14 @@
     def emit_op_guard_exception(self, op, arglocs, regalloc, fcond):
         loc, loc1, resloc, pos_exc_value, pos_exception = arglocs[:5]
         failargs = arglocs[5:]
-        self.mc.LDR_ri(loc1.value, loc1.value)
+        self.mc.gen_load_int(loc1.value, pos_exception.value)
+        self.mc.LDR_ri(r.ip.value, loc1.value)
 
-        self.mc.CMP_rr(loc1.value, loc.value)
+        self.mc.CMP_rr(r.ip.value, loc.value)
         self._emit_guard(op, failargs, c.EQ, save_exc=True)
-        self.mc.gen_load_int(loc1.value, pos_exc_value.value, fcond)
+        self.mc.gen_load_int(loc.value, pos_exc_value.value, fcond)
         if resloc:
-            self.mc.LDR_ri(resloc.value, loc1.value)
-        self.mc.gen_load_int(loc.value, pos_exception.value, fcond)
+            self.mc.LDR_ri(resloc.value, loc.value)
         self.mc.MOV_ri(r.ip.value, 0)
         self.mc.STR_ri(r.ip.value, loc.value)
         self.mc.STR_ri(r.ip.value, loc1.value)

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py	Mon Dec 13 11:56:20 2010
@@ -304,15 +304,14 @@
         arg0 = ConstInt(rffi.cast(lltype.Signed, op.getarg(0).getint()))
         loc, box = self._ensure_value_is_boxed(arg0)
         boxes.append(box)
-        loc1, box = self._ensure_value_is_boxed(
-                    ConstInt(self.assembler.cpu.pos_exception()), boxes)
+        box = TempBox()
+        loc1 = self.force_allocate_reg(box, boxes)
         boxes.append(box)
         if op.result in self.longevity:
             resloc = self.force_allocate_reg(op.result, boxes)
             boxes.append(resloc)
         else:
             resloc = None
-        # There is some redundancy here ?!
         pos_exc_value = imm(self.assembler.cpu.pos_exc_value())
         pos_exception = imm(self.assembler.cpu.pos_exception())
         arglocs = self._prepare_guard(op, [loc, loc1, resloc, pos_exc_value, pos_exception])