[pypy-svn] r74736 - in pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86: . test

jcreigh at codespeak.net jcreigh at codespeak.net
Tue May 25 17:15:21 CEST 2010


Author: jcreigh
Date: Tue May 25 17:15:19 2010
New Revision: 74736

Modified:
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py
   pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
Log:
add SHL/SHR/SAR to rx86

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py	Tue May 25 17:15:19 2010
@@ -634,6 +634,9 @@
     genop_int_and = _binaryop("AND", True)
     genop_int_or  = _binaryop("OR", True)
     genop_int_xor = _binaryop("XOR", True)
+    genop_int_lshift = _binaryop("SHL")
+    genop_int_rshift = _binaryop("SAR")
+    genop_uint_rshift = _binaryop("SHR")
     genop_float_add = _binaryop("ADDSD", True)
     genop_float_sub = _binaryop('SUBSD')
     genop_float_mul = _binaryop('MULSD', True)
@@ -733,24 +736,6 @@
     def genop_cast_int_to_float(self, op, arglocs, resloc):
         self.mc.CVTSI2SD(resloc, arglocs[0])
 
-    def genop_int_lshift(self, op, arglocs, resloc):
-        loc, loc2 = arglocs
-        if loc2 is ecx:
-            loc2 = cl
-        self.mc.SHL(loc, loc2)
-
-    def genop_int_rshift(self, op, arglocs, resloc):
-        loc, loc2 = arglocs
-        if loc2 is ecx:
-            loc2 = cl
-        self.mc.SAR(loc, loc2)
-
-    def genop_uint_rshift(self, op, arglocs, resloc):
-        loc, loc2 = arglocs
-        if loc2 is ecx:
-            loc2 = cl
-        self.mc.SHR(loc, loc2)
-
     def genop_guard_int_is_true(self, op, guard_op, addr, arglocs, resloc):
         guard_opnum = guard_op.opnum
         self.mc.CMP(arglocs[0], imm(0))

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py	Tue May 25 17:15:19 2010
@@ -135,6 +135,9 @@
     ADD = _binaryop('ADD')
     OR  = _binaryop('OR')
     XOR = _binaryop('XOR')
+    SHL = _binaryop('SHL')
+    SHR = _binaryop('SHR')
+    SAR = _binaryop('SAR')
     TEST = _binaryop('TEST')
 
     AND = _binaryop('AND')

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py	Tue May 25 17:15:19 2010
@@ -333,6 +333,23 @@
 
     return INSN
 
+def shifts(mod_field):
+    modrm = chr(0xC0 | (mod_field << 3))
+    shift_once = insn(rex_w, '\xD1', register(1), modrm)
+    shift_r_by_cl = insn(rex_w, '\xD3', register(1), modrm)
+    shift_ri8 = insn(rex_w, '\xC1', register(1), modrm, immediate(2, 'b'))
+
+    def shift_ri(mc, reg, immed):
+        if immed == 1:
+            shift_once(mc, reg)
+        else:
+            shift_ri8(mc, reg, immed)
+
+    def shift_rr(mc, reg1, reg2):
+        assert reg2 == R.ecx
+        shift_r_by_cl(mc, reg1)
+
+    return (shift_ri, shift_rr)
 # ____________________________________________________________
 
 
@@ -423,6 +440,10 @@
     def IMUL_ri(self, reg, immed):
         self.IMUL_rri(reg, reg, immed)
 
+    SHL_ri, SHL_rr = shifts(4)
+    SHR_ri, SHR_rr = shifts(5)
+    SAR_ri, SAR_rr = shifts(7)
+
     # ------------------------------ Misc stuff ------------------------------
 
     NOP = insn('\x90')

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py	Tue May 25 17:15:19 2010
@@ -16,6 +16,10 @@
     def tell(self):
         return 0x76543210 + len(self.buffer)
 
+def assert_encodes_as(code_builder_cls, insn_name, args, expected_encoding):
+    s = code_builder_cls()
+    getattr(s, insn_name)(*args)
+    assert s.getvalue() == expected_encoding
 
 class CodeBuilder32(CodeBuilderMixin, X86_32_CodeBuilder):
     pass
@@ -155,6 +159,20 @@
     s.IMUL_rri(ebx, ecx, 0x2A)
     assert s.getvalue() == '\x6B\xD9\x2A'
 
+def test_shifts():
+    cb = CodeBuilder32
+    assert_encodes_as(cb, 'SHL_ri', (edx, 1), '\xD1\xE2')
+    assert_encodes_as(cb, 'SHL_ri', (edx, 5), '\xC1\xE2\x05')
+    assert_encodes_as(cb, 'SHL_rr', (edx, ecx), '\xD3\xE2')
+
+    assert_encodes_as(cb, 'SHR_ri', (edx, 1), '\xD1\xEA')
+    assert_encodes_as(cb, 'SHR_ri', (edx, 5), '\xC1\xEA\x05')
+    assert_encodes_as(cb, 'SHR_rr', (edx, ecx), '\xD3\xEA')
+
+    assert_encodes_as(cb, 'SAR_ri', (edx, 1), '\xD1\xFA')
+    assert_encodes_as(cb, 'SAR_ri', (edx, 5), '\xC1\xFA\x05')
+    assert_encodes_as(cb, 'SAR_rr', (edx, ecx), '\xD3\xFA')
+
 class CodeBuilder64(CodeBuilderMixin, X86_64_CodeBuilder):
     pass
 

Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py	(original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py	Tue May 25 17:15:19 2010
@@ -222,6 +222,9 @@
                 return []   # MOV [immediate], EAX: there is a special encoding
             if methname == 'SET_ir':
                 py.test.skip("SET_ir: must be tested manually")
+            if methname.startswith('SHL') or methname.startswith('SAR') or methname.startswith('SHR'):
+                # XXX: Would be nice to test these automatically
+                py.test.skip('Shifts must be tested manually')
             return [args]
 
     def get_code_checker_class(self):



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