[pypy-svn] r74747 - in pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86: . test
jcreigh at codespeak.net
jcreigh at codespeak.net
Tue May 25 20:54:20 CEST 2010
Author: jcreigh
Date: Tue May 25 20:54:18 2010
New Revision: 74747
Modified:
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py
Log:
add concept of "byte registers" to rx86 to try to avoid confusion
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py Tue May 25 20:54:18 2010
@@ -543,14 +543,14 @@
self.mc.UCOMISD(arglocs[0], arglocs[1])
rl = result_loc.lowest8bits()
rh = result_loc.higher8bits()
- getattr(self.mc, 'SET' + cond)(rl)
+ self.mc.SET_ir(rx86.Conditions[cond], rl.value)
if is_ne:
- self.mc.SETP(rh)
- self.mc.OR(rl, rh)
+ self.mc.SET_ir(rx86.Conditions['P'], rh.value)
+ self.mc.OR8_rr(rl.value, rh.value)
else:
- self.mc.SETNP(rh)
- self.mc.AND(rl, rh)
- self.mc.MOVZX(result_loc, rl)
+ self.mc.SET_ir(rx86.Conditions['NP'], rh.value)
+ self.mc.AND8_rr(rl.value, rh.value)
+ self.mc.MOVZX8_rr(result_loc.value, rl.value)
return genop_cmp
def _cmpop_guard(cond, rev_cond, false_cond, false_rev_cond):
@@ -720,15 +720,8 @@
return self.implement_guard(addr)
def genop_float_is_true(self, op, arglocs, resloc):
- loc0, loc1 = arglocs
- self.mc.XORPD(loc0, loc0)
- self.mc.UCOMISD(loc0, loc1)
- rl = resloc.lowest8bits()
- rh = resloc.higher8bits()
- self.mc.SETNE(rl)
- self.mc.SETP(rh)
- self.mc.OR(rl, rh)
- self.mc.MOVZX(resloc, rl)
+ self.mc.XORPD(arglocs[0], arglocs[0])
+ self.genop_float_ne(op, arglocs, resloc)
def genop_cast_float_to_int(self, op, arglocs, resloc):
self.mc.CVTTSD2SI(resloc, arglocs[0])
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py Tue May 25 20:54:18 2010
@@ -51,10 +51,12 @@
return rx86.R.names[self.value]
def lowest8bits(self):
- # XXX: Only handling i386 al, cl, dl, bl for now
- assert self.value < 4
assert not self.is_xmm
- return self
+ return RegLoc(rx86.low_byte(self.value), False)
+
+ def higher8bits(self):
+ assert not self.is_xmm
+ return RegLoc(rx86.high_byte(self.value), False)
def location_code(self):
return 'r'
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py Tue May 25 20:54:18 2010
@@ -4,10 +4,15 @@
from pypy.rlib.unroll import unrolling_iterable
from pypy.rpython.lltypesystem import rffi
+BYTE_REG_FLAG = 0x20
+
class R(object):
# the following are synonyms for rax, rcx, etc. on 64 bits
eax, ecx, edx, ebx, esp, ebp, esi, edi = range(8)
+ # 8-bit registers
+ al, cl, dl, bl, ah, ch, dh, bh = [reg | BYTE_REG_FLAG for reg in range(8)]
+
# xmm registers
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 = range(8)
@@ -15,10 +20,23 @@
r8, r9, r10, r11, r12, r13, r14, r15 = range(8, 16)
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15 = range(8, 16)
+ # These replace ah, ch, dh, bh when the REX-prefix is used
+ spl, bpl, sil, dil = ah, ch, dh, bh
+
+ # Low-byte of extra registers
+ r8l, r9l, r10l, r11l, r12l, r13l, r14l, r15l = [reg | BYTE_REG_FLAG for reg in range(8, 16)]
+
names = ['eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi',
'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15']
xmmnames = ['xmm%d' % i for i in range(16)]
+def low_byte(reg):
+ assert 0 <= reg < 4
+ return reg | BYTE_REG_FLAG
+
+def high_byte(reg):
+ assert 0 <= reg < 4
+ return (reg + 4) | BYTE_REG_FLAG
def single_byte(value):
return -128 <= value < 128
@@ -63,6 +81,16 @@
assert factor in (1, 8)
return encode_register, argnum, factor, rex_register
+ at specialize.arg(2)
+def encode_byte_register(mc, reg, factor, orbyte):
+ assert reg & BYTE_REG_FLAG
+ return encode_register(mc, reg & ~BYTE_REG_FLAG, factor, orbyte)
+
+def byte_register(argnum, factor=1):
+ assert factor in (1, 8)
+ return encode_byte_register, argnum, factor, rex_register
+
+
# ____________________________________________________________
# Encode a constant in the orbyte
@@ -400,8 +428,9 @@
MOV_jr = insn(rex_w, '\x89', register(2,8), '\x05', immediate(1))
MOV_ji = insn(rex_w, '\xC7', '\x05', immediate(1), immediate(2))
- MOV8_mr = insn(rex_w, '\x88', register(2, 8), mem_reg_plus_const(1))
+ MOV8_mr = insn(rex_w, '\x88', byte_register(2, 8), mem_reg_plus_const(1))
+ MOVZX8_rr = insn(rex_w, '\x0F\xB6', register(1,8), byte_register(2))
MOVZX8_rm = insn(rex_w, '\x0F\xB6', register(1,8), mem_reg_plus_const(2))
MOVZX8_ra = insn(rex_w, '\x0F\xB6', register(1,8), mem_reg_plus_scaled_reg_plus_const(2))
@@ -425,6 +454,10 @@
CMP_ji32 = insn(rex_w, '\x81', '\x3D', immediate(1), immediate(2))
CMP_ji = select_8_or_32_bit_immed(CMP_ji8, CMP_ji32)
+ AND8_rr = insn(rex_w, '\x20', byte_register(1), byte_register(2,8), '\xC0')
+
+ OR8_rr = insn(rex_w, '\x08', byte_register(1), byte_register(2,8), '\xC0')
+
NEG_r = insn(rex_w, '\xF7', register(1), '\xD8')
DIV_r = insn(rex_w, '\xF7', register(1), '\xF0')
@@ -469,7 +502,8 @@
# We need to be consistent.
J_il8 = insn(immediate(1, 'o'), '\x70', immediate(2, 'b'))
J_il = insn('\x0F', immediate(1,'o'), '\x80', relative(2))
- SET_ir = insn('\x0F', immediate(1,'o'),'\x90', register(2), '\xC0')
+
+ SET_ir = insn('\x0F', immediate(1,'o'),'\x90', byte_register(2), '\xC0')
# The 64-bit version of this, CQO, is defined in X86_64_CodeBuilder
CDQ = insn(rex_nw, '\x99')
@@ -590,15 +624,15 @@
py.test.skip("MOVSD_rj unsupported")
def MOVSD_jr(self, xmm_reg, mem_immed):
py.test.skip("MOVSD_jr unsupported")
- def ADDSD_rj(self, xxm_reg, mem_immed):
+ def ADDSD_rj(self, xmm_reg, mem_immed):
py.test.skip("ADDSD_rj unsupported")
- def SUBSD_rj(self, xxm_reg, mem_immed):
+ def SUBSD_rj(self, xmm_reg, mem_immed):
py.test.skip("SUBSD_rj unsupported")
- def MULSD_rj(self, xxm_reg, mem_immed):
+ def MULSD_rj(self, xmm_reg, mem_immed):
py.test.skip("MULSD_rj unsupported")
- def DIVSD_rj(self, xxm_reg, mem_immed):
+ def DIVSD_rj(self, xmm_reg, mem_immed):
py.test.skip("DIVSD_rj unsupported")
- def UCOMISD_rj(self, xxm_reg, mem_immed):
+ def UCOMISD_rj(self, xmm_reg, mem_immed):
py.test.skip("UCOMISD_rj unsupported")
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py Tue May 25 20:54:18 2010
@@ -121,7 +121,7 @@
def test_set_ir():
s = CodeBuilder32()
- s.SET_ir(5, 2)
+ s.SET_ir(5, dl)
assert s.getvalue() == '\x0F\x95\xC2'
def test_xchg_rj():
@@ -173,6 +173,12 @@
assert_encodes_as(cb, 'SAR_ri', (edx, 5), '\xC1\xFA\x05')
assert_encodes_as(cb, 'SAR_rr', (edx, ecx), '\xD3\xFA')
+def test_and8_rr():
+ assert_encodes_as(CodeBuilder32, 'AND8_rr', (bl, bh), '\x20\xFB')
+
+def test_or8_rr():
+ assert_encodes_as(CodeBuilder32, 'OR8_rr', (bl, bh), '\x08\xFB')
+
class CodeBuilder64(CodeBuilderMixin, X86_64_CodeBuilder):
pass
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