[pypy-svn] r78689 - pypy/branch/arm-backend/pypy/jit/backend/arm

david at codespeak.net david at codespeak.net
Thu Nov 4 11:15:34 CET 2010


Author: david
Date: Thu Nov  4 11:15:32 2010
New Revision: 78689

Added:
   pypy/branch/arm-backend/pypy/jit/backend/arm/shift.py
Modified:
   pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
Log:
Implement guard_overflow and int_mul_ovf

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py	Thu Nov  4 11:15:32 2010
@@ -165,7 +165,7 @@
                             | (rn & 0xF))
 
     elif 'long' in table and table['long']:
-       def f(self, rdhi, rdlo, rn, rm, cond=cond.AL):
+       def f(self, rdlo, rdhi, rn, rm, cond=cond.AL):
             assert rdhi != rdlo
             self.write32(n
                         | cond << 28

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py	Thu Nov  4 11:15:32 2010
@@ -1,6 +1,7 @@
 from pypy.jit.backend.arm import conditions as c
 from pypy.jit.backend.arm import locations
 from pypy.jit.backend.arm import registers as r
+from pypy.jit.backend.arm import shift
 from pypy.jit.backend.arm.arch import (WORD, FUNC_ALIGN, arm_int_div,
                                         arm_int_div_sign, arm_int_mod_sign, arm_int_mod)
 
@@ -83,6 +84,16 @@
         regalloc.possibly_free_vars_for_op(op)
         return fcond
 
+    #ref: http://blogs.arm.com/software-enablement/detecting-overflow-from-mul/
+    def emit_op_int_mul_ovf(self, op, regalloc, fcond):
+        reg1 = regalloc.make_sure_var_in_reg(op.getarg(0), imm_fine=False)
+        reg2 = regalloc.make_sure_var_in_reg(op.getarg(1), imm_fine=False)
+        res = regalloc.force_allocate_reg(op.result)
+        self.mc.SMULL(res.value, r.ip.value, reg1.value, reg2.value, cond=fcond)
+        self.mc.CMP_rr(r.ip.value, res.value, shifttype=shift.ASR, s=31, cond=fcond)
+        regalloc.possibly_free_vars_for_op(op)
+        return fcond
+
     emit_op_int_floordiv = gen_emit_op_by_helper_call('DIV')
     emit_op_int_mod = gen_emit_op_by_helper_call('MOD')
     emit_op_uint_floordiv = gen_emit_op_by_helper_call('UDIV')
@@ -111,6 +122,7 @@
     emit_op_int_sub_ovf = emit_op_int_sub
 
 
+
 class UnaryIntOpAssembler(object):
     emit_op_int_is_true = gen_emit_op_unary_cmp(c.NE, c.EQ)
     emit_op_int_is_zero = gen_emit_op_unary_cmp(c.EQ, c.NE)
@@ -160,6 +172,9 @@
     def emit_op_guard_no_overflow(self, op, regalloc, fcond):
         return self._emit_guard(op, regalloc, c.VS)
 
+    def emit_op_guard_overflow(self, op, regalloc, fcond):
+        return self._emit_guard(op, regalloc, c.VC)
+
 class OpAssembler(object):
     _mixin_ = True
 

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/shift.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/shift.py	Thu Nov  4 11:15:32 2010
@@ -0,0 +1,6 @@
+# According to A8.4
+LSL = 0xB00
+LSR = 0xB01
+ASR = 0xB10
+ROR = 0xB11
+RRX = 0xB11 # with imm = 0



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