[pypy-svn] r78825 - pypy/branch/arm-backend/pypy/jit/backend/arm
david at codespeak.net
david at codespeak.net
Sun Nov 7 17:50:29 CET 2010
Author: david
Date: Sun Nov 7 17:50:27 2010
New Revision: 78825
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py
pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py
Log:
Implement setfield_gc and getfield_gc operations
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py Sun Nov 7 17:50:27 2010
@@ -5,7 +5,8 @@
from pypy.jit.backend.arm.codebuilder import ARMv7Builder, ARMv7InMemoryBuilder
from pypy.jit.backend.arm.regalloc import ARMRegisterManager, ARMFrameManager
from pypy.jit.backend.llsupport.regalloc import compute_vars_longevity
-from pypy.jit.metainterp.history import ConstInt, BoxInt, Box, BasicFailDescr
+from pypy.jit.metainterp.history import (ConstInt, BoxInt, Box, BasicFailDescr,
+ INT, REF, FLOAT)
from pypy.jit.metainterp.resoperation import rop
from pypy.rlib import rgc
from pypy.rpython.annlowlevel import llhelper
@@ -13,18 +14,20 @@
from pypy.jit.backend.arm.opassembler import (GuardOpAssembler,
IntOpAsslember,
OpAssembler,
- UnaryIntOpAssembler)
+ UnaryIntOpAssembler,
+ FieldOpAssembler)
# XXX Move to llsupport
from pypy.jit.backend.x86.support import values_array
class AssemblerARM(GuardOpAssembler, IntOpAsslember,
- OpAssembler, UnaryIntOpAssembler):
+ OpAssembler, UnaryIntOpAssembler, FieldOpAssembler):
def __init__(self, cpu, failargs_limit=1000):
self.mc = ARMv7Builder()
self.cpu = cpu
self.fail_boxes_int = values_array(lltype.Signed, failargs_limit)
+ self.fail_boxes_ptr = values_array(llmemory.GCREF, failargs_limit)
self._debug_asm = True
self._exit_code_addr = self.mc.curraddr()
@@ -58,11 +61,16 @@
i += 1
fail_index += 1
res = enc[i]
- if res == '\xFE':
- continue
if res == '\xFF':
break
+ if res == '\xFE':
+ continue
+
+ group = res
+ i += 1
+ res = enc[i]
if res == '\xFD':
+ assert group == '\xEF'
# imm value
value = self.decode32(enc, i+1)
i += 4
@@ -75,7 +83,13 @@
reg = ord(enc[i])
value = self.decode32(stack, reg*WORD)
- self.fail_boxes_int.setitem(fail_index, value)
+ if group == '\xEF': # INT
+ self.fail_boxes_int.setitem(fail_index, value)
+ elif group == '\xEE': # REF
+ self.fail_boxes_ptr.setitem(fail_index, rffi.cast(llmemory.GCREF, value))
+ else:
+ assert 0, 'unknown type'
+
assert enc[i] == '\xFF'
descr = self.decode32(enc, i+1)
@@ -114,6 +128,10 @@
def _gen_path_to_exit_path(self, op, args, regalloc, fcond=c.AL):
"""
+ types:
+ \xEE = REF
+ \xEF = INT
+ location:
\xFC = stack location
\xFD = imm location
\xFE = Empty arg
@@ -122,21 +140,31 @@
box = Box()
reg = regalloc.force_allocate_reg(box)
# XXX free this memory
+ # XXX allocate correct amount of memory
mem = lltype.malloc(rffi.CArray(lltype.Char), (len(args)+5)*4, flavor='raw')
i = 0
j = 0
while(i < len(args)):
if args[i]:
loc = regalloc.loc(args[i])
+ if args[i].type == INT:
+ mem[j] = '\xEF'
+ j += 1
+ elif args[i].type == REF:
+ mem[j] = '\xEE'
+ j += 1
+ else:
+ assert 0, 'unknown type'
+
if loc.is_reg():
mem[j] = chr(loc.value)
j += 1
elif loc.is_imm():
+ assert args[i].type == INT
mem[j] = '\xFD'
self.encode32(mem, j+1, loc.getint())
j += 5
else:
- #print 'Encoding a stack location'
mem[j] = '\xFC'
self.encode32(mem, j+1, loc.position)
j += 5
@@ -178,8 +206,14 @@
def gen_bootstrap_code(self, inputargs, regalloc, looptoken):
regs = []
for i in range(len(inputargs)):
- reg = regalloc.force_allocate_reg(inputargs[i])
- addr = self.fail_boxes_int.get_addr_for_num(i)
+ loc = inputargs[i]
+ reg = regalloc.force_allocate_reg(loc)
+ if loc.type == REF:
+ addr = self.fail_boxes_ptr.get_addr_for_num(i)
+ elif loc.type == INT:
+ addr = self.fail_boxes_int.get_addr_for_num(i)
+ else:
+ raise ValueError
self.mc.gen_load_int(reg.value, addr)
self.mc.LDR_ri(reg.value, reg.value)
regs.append(reg)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py Sun Nov 7 17:50:27 2010
@@ -10,6 +10,7 @@
gen_emit_op_ri, gen_emit_cmp_op)
from pypy.jit.backend.arm.codebuilder import ARMv7Builder, ARMv7InMemoryBuilder
from pypy.jit.backend.arm.regalloc import ARMRegisterManager
+from pypy.jit.backend.llsupport.descr import BaseFieldDescr, BaseArrayDescr
from pypy.jit.backend.llsupport.regalloc import compute_vars_longevity, TempBox
from pypy.jit.metainterp.history import ConstInt, BoxInt, Box, BasicFailDescr
from pypy.jit.metainterp.resoperation import rop
@@ -220,3 +221,46 @@
regalloc.force_allocate_reg(op.result, selected_reg=r.r0)
regalloc.after_call(op.result)
regalloc.possibly_free_vars(locs)
+
+class FieldOpAssembler(object):
+
+ def emit_op_setfield_gc(self, op, regalloc, fcond):
+ ofs, size, ptr = self._unpack_fielddescr(op.getdescr())
+ #ofs_loc = regalloc.make_sure_var_in_reg(ConstInt(ofs))
+ #size_loc = regalloc.make_sure_var_in_reg(ofs)
+ base_loc = regalloc.make_sure_var_in_reg(op.getarg(0), imm_fine=False)
+ value_loc = regalloc.make_sure_var_in_reg(op.getarg(1), imm_fine=False)
+ if size == 4:
+ f = self.mc.STR_ri
+ elif size == 2:
+ f = self.mc.STRH_ri
+ elif size == 1:
+ f = self.mc.STRB_ri
+ else:
+ assert 0
+ f(value_loc.value, base_loc.value, ofs)
+ return fcond
+
+ def emit_op_getfield_gc(self, op, regalloc, fcond):
+ ofs, size, ptr = self._unpack_fielddescr(op.getdescr())
+ # ofs_loc = regalloc.make_sure_var_in_reg(ConstInt(ofs))
+ base_loc = regalloc.make_sure_var_in_reg(op.getarg(0), imm_fine=False)
+ res = regalloc.force_allocate_reg(op.result)
+ if size == 4:
+ f = self.mc.LDR_ri
+ elif size == 2:
+ f = self.mc.LDRH_ri
+ elif size == 1:
+ f = self.mc.LDRB_ri
+ else:
+ assert 0
+ f(res.value, base_loc.value, ofs)
+ return fcond
+
+ #XXX from ../x86/regalloc.py:791
+ def _unpack_fielddescr(self, fielddescr):
+ assert isinstance(fielddescr, BaseFieldDescr)
+ ofs = fielddescr.offset
+ size = fielddescr.get_field_size(self.cpu.translate_support_code)
+ ptr = fielddescr.is_pointer_field()
+ return ofs, size, ptr
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py Sun Nov 7 17:50:27 2010
@@ -2,6 +2,8 @@
RegisterManager, compute_vars_longevity
from pypy.jit.backend.arm import registers as r
from pypy.jit.backend.arm import locations
+from pypy.jit.metainterp.history import ConstInt
+from pypy.rpython.lltypesystem import rffi, lltype
class ARMRegisterManager(RegisterManager):
all_regs = r.all_regs
@@ -15,14 +17,19 @@
def update_bindings(self, enc, inputargs):
j = 0
for i in range(len(inputargs)):
- # XXX decode imm and and stack locs
+ # XXX decode imm and and stack locs and REFs
while enc[j] == '\xFE':
j += 1
+ assert enc[j] == '\xEF'
+ j += 1
self.force_allocate_reg(inputargs[i], selected_reg=r.all_regs[ord(enc[j])])
j += 1
def convert_to_imm(self, c):
- return locations.ImmLocation(c.value)
+ if isinstance(c, ConstInt):
+ return locations.ImmLocation(c.value)
+ else:
+ return locations.ImmLocation(rffi.cast(lltype.Signed, c.value))
def call_result_location(self, v):
return r.r0
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py Sun Nov 7 17:50:27 2010
@@ -13,6 +13,6 @@
all_regs = [r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10]
caller_resp = [r0, r1, r2, r3]
-callee_resp = [r4, r5, r6, r7, r8, r9, r10, r11]
+callee_resp = [r4, r5, r6, r7, r8, r9, r10, fp]
callee_saved_registers = callee_resp+[lr]
callee_restored_registers = callee_resp+[pc]
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py Sun Nov 7 17:50:27 2010
@@ -24,9 +24,15 @@
def set_future_value_int(self, index, intvalue):
self.assembler.fail_boxes_int.setitem(index, intvalue)
+ def set_future_value_ref(self, index, ptrvalue):
+ self.assembler.fail_boxes_ptr.setitem(index, ptrvalue)
+
def get_latest_value_int(self, index):
return self.assembler.fail_boxes_int.getitem(index)
+ def get_latest_value_ref(self, index):
+ return self.assembler.fail_boxes_ptr.getitem(index)
+
def get_latest_value_count(self):
return self.assembler.fail_boxes_count
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