[pypy-svn] r77631 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test

david at codespeak.net david at codespeak.net
Tue Oct 5 21:25:14 CEST 2010


Author: david
Date: Tue Oct  5 21:25:08 2010
New Revision: 77631

Added:
   pypy/branch/arm-backend/pypy/jit/backend/arm/
   pypy/branch/arm-backend/pypy/jit/backend/arm/__init__.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/conditions.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/__init__.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/gen.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
Log:
basic encoding for some arm instructions and infrastructure for testing


Added: pypy/branch/arm-backend/pypy/jit/backend/arm/__init__.py
==============================================================================

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	Tue Oct  5 21:25:08 2010
@@ -0,0 +1,79 @@
+import conditions as cond
+from pypy.rlib.rmmap import alloc
+from pypy.rpython.lltypesystem import lltype, rffi
+
+class ARMv7Builder(object):
+
+    def __init__(self):
+        self._data = alloc(1024)
+        self._pos = 0
+
+    def LDR_ri(self, rt, rn, imm=0, cond=cond.AL):
+        #  XXX U and P bits are not encoded yet
+        self.write32(cond << 28
+                        | 5 << 24
+                        | 9 << 20
+                        | (rn & 0xF) << 16
+                        | (rt & 0xF) << 12
+                        | (imm & 0xFFF))
+
+    def ADD_ri(self, rt, rn, imm, cond=cond.AL):
+        # XXX S bit
+        self.write32(cond << 28
+                        | 2 << 24
+                        | 8 << 20
+                        | (rn & 0xF) << 16
+                        | (rt & 0xF) << 12
+                        | (imm & 0xFFF))
+    def MOV_ri(self, rt, imm=0, cond=cond.AL):
+        # XXX Check the actual allowed size for imm
+        # XXX S bit
+        self.write32(cond << 28
+                    | 0x3 << 24
+                    | 0xA << 20
+                    #| 0x0 << 16
+                    | (rt & 0xF) << 12
+                    | (imm & 0xFFF))
+
+    def STR_ri(self, rt, rn, imm=0, cond=cond.AL):
+        self.write32(cond << 28
+                    | 0x5 << 24
+                    | 0x8 << 20
+                    | (rn & 0xF) << 16
+                    | (rt & 0xF) << 12
+                    | (imm & 0xFFF))
+
+    def ASR_ri(self, rd, rm, imm=0, cond=cond.AL, s=0):
+        self.write32(cond << 28
+                    | 0xD << 21
+                    | (s & 0x1) << 20
+                    | (rd & 0xF) << 12
+                    | (imm & 0x1F) << 7
+                    | 0x4 << 4
+                    | (rm & 0xF))
+
+    #XXX encode shifttype correctly
+    def ORR_rr(self, rd, rn, rm, imm=0, cond=cond.AL, s=0, shifttype=0):
+        self.write32(cond << 28
+                    | 0x3 << 23
+                    | (s & 0x1) << 20
+                    | (rn & 0xFF) << 16
+                    | (rd & 0xFF) << 12
+                    | (imm & 0x1F) << 7
+                    | (shifttype & 0x3) << 5
+                    | (rm & 0xFF))
+
+    def write32(self, word):
+        self.writechar(chr(word & 0xFF))
+        self.writechar(chr((word >> 8) & 0xFF))
+        self.writechar(chr((word >> 16) & 0xFF))
+        self.writechar(chr((word >> 24) & 0xFF))
+
+    def writechar(self, char):
+        self._data[self._pos] = char
+        self._pos += 1
+
+    def baseaddr(self):
+        return rffi.cast(lltype.Signed, self._data)
+
+

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/conditions.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/conditions.py	Tue Oct  5 21:25:08 2010
@@ -0,0 +1,15 @@
+EQ = 0x0
+NE = 0x1
+CS = 0x2
+CC = 0x3
+MI = 0x4
+PL = 0x5
+VS = 0x6
+VC = 0x7
+HI = 0x8
+LS = 0x9
+GE = 0xA
+LT = 0xB
+GT = 0xC
+LE = 0xD
+AL = 0xE

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py	Tue Oct  5 21:25:08 2010
@@ -0,0 +1,6 @@
+r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 = range(16)
+# aliases for registers
+ip = 12
+sp = 13
+lr = 14
+pc = 15

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/test/__init__.py
==============================================================================

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/test/gen.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/gen.py	Tue Oct  5 21:25:08 2010
@@ -0,0 +1,52 @@
+import os
+import tempfile
+class ASMInstruction(object):
+
+    if os.uname()[0] == 'Darwin':
+        asm = '~/Code/arm-jit/android/android-ndk-r4b//build/prebuilt/darwin-x86/arm-eabi-4.4.0/arm-eabi/bin/as'
+    else:
+        asm = 'as'
+    asm_opts = '-mcpu=cortex-a8 -march=armv7'
+    body = """.section .text
+.arm
+.global main
+main:
+    .ascii "START"
+    %s
+    .ascii "END"
+"""
+    begin_tag = 'START'
+    end_tag = 'END'
+
+    def __init__(self, instr):
+        self.instr = instr
+        self.file = tempfile.NamedTemporaryFile(mode='w')
+        self.name = self.file.name
+        self.tmpdir = os.path.dirname(self.name)
+
+    def encode(self):
+        f = open("%s/a.out" % (self.tmpdir),'rb')
+        data = f.read()
+        f.close()
+        i = data.find(self.begin_tag)
+        assert i>=0
+        j = data.find(self.end_tag, i)
+        assert j>=0
+        as_code = data[i+len(self.begin_tag):j]
+        return as_code
+
+
+
+    def assemble(self, *args):
+        res = self.body % (self.instr)
+        self.file.write(res)
+        self.file.flush()
+        os.system("%s %s %s -o %s/a.out" % (self.asm, self.asm_opts, self.name, self.tmpdir))
+
+    def __del__(self):
+        self.file.close()
+
+def assemble(instr):
+    a = ASMInstruction(instr)
+    a.assemble(instr)
+    return a.encode()

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	Tue Oct  5 21:25:08 2010
@@ -0,0 +1,58 @@
+from pypy.jit.backend.arm import registers as r
+from pypy.jit.backend.arm import codebuilder
+from gen import assemble
+import py
+class CodeBuilder(codebuilder.ARMv7Builder):
+    def __init__(self):
+        self.buffer = []
+
+    def writechar(self, char):
+        self.buffer.append(char)
+
+    def hexdump(self):
+        return ''.join(self.buffer)
+
+class TestInstrCodeBuilder(object):
+    def setup_method(self, ffuu_method):
+        self.cb = CodeBuilder()
+
+    def test_ldr(self):
+        self.cb.LDR_ri(r.r0, r.r1)
+        self.assert_equal("LDR r0, [r1]")
+
+    def test_add_ri(self):
+        self.cb.ADD_ri(r.r0, r.r1, 1)
+        self.assert_equal("ADD r0, r1, #1")
+
+    def test_mov_ri(self):
+        self.cb.MOV_ri(r.r9, 123)
+        self.assert_equal("MOV r9, #123")
+
+    def test_mov_ri2(self):
+        self.cb.MOV_ri(r.r9, 255)
+        self.assert_equal("MOV r9, #255")
+
+    def test_mov_ri_max(self):
+        py.test.skip("Check the actual largest thing")
+        self.cb.MOV_ri(r.r9, 0xFFF)
+        self.assert_equal("MOV r9, #4095")
+
+    def test_str_ri(self):
+        self.cb.STR_ri(r.r9, r.r14)
+        self.assert_equal("STR r9, [r14]")
+
+    def test_asr_ri(self):
+        self.cb.ASR_ri(r.r7, r.r5, 24)
+        self.assert_equal('ASR r7, r5, #24')
+
+    def test_orr_rr_no_shift(self):
+        self.cb.ORR_rr(r.r0, r.r7,r.r12)
+        self.assert_equal('ORR r0, r7, r12')
+
+    def test_orr_rr_lsl_8(self):
+        self.cb.ORR_rr(r.r0, r.r7,r.r12, 8)
+        self.assert_equal('ORR r0, r7, r12, lsl #8')
+
+    def assert_equal(self, asm):
+        assert self.cb.hexdump() == assemble(asm)
+



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