[pypy-svn] r77632 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test

david at codespeak.net david at codespeak.net
Tue Oct 5 21:33:11 CEST 2010


Author: david
Date: Tue Oct  5 21:33:10 2010
New Revision: 77632

Added:
   pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_runner.py
Log:
simple implementation of cpu and assembler to pass test_compile_linear_loop in runner_test


Added: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py	Tue Oct  5 21:33:10 2010
@@ -0,0 +1,52 @@
+from pypy.jit.backend.arm.codebuilder import ARMv7Builder
+from pypy.jit.backend.arm import registers as r
+from pypy.jit.backend.arm.regalloc import RegAlloc, ARMRegisterManager
+from pypy.jit.metainterp.resoperation import rop
+from pypy.rpython.lltypesystem import lltype
+# XXX Move to llsupport
+from pypy.jit.backend.x86.support import values_array
+
+
+class AssemblerARM(object):
+
+    def __init__(self, cpu, failargs_limit=1000):
+        self.mc = ARMv7Builder()
+        self.cpu = cpu
+        self.fail_boxes_int = values_array(lltype.Signed, failargs_limit)
+
+    def assemble_loop(self, inputargs, operations, looptoken):
+        assert len(inputargs) == 1
+        reg = 0
+        self.gen_preamble()
+        addr = self.fail_boxes_int.get_addr_for_num(0)
+        self.gen_load_int(r.r3, addr)
+        self.mc.LDR_ri(r.r2, r.r3)
+        for op in operations:
+            if op.getopnum() == rop.INT_ADD:
+                self.mc.ADD_ri(r.r1, r.r2, op.getarg(1).getint())
+            elif op.getopnum() == rop.FINISH:
+                n = self.cpu.get_fail_descr_number(op.getdescr())
+                self.mc.MOV_ri(r.r0, n)
+                self.mc.STR_ri(r.r1, r.r3)
+                self.gen_out()
+
+    def gen_out(self):
+        self.mc.write32(0xe50b3010) #        str     r3, [fp, #-16]
+        self.mc.write32(0xe51b3010) #        ldr     r3, [fp, #-16]
+        #self.mc.write32(0xe1a00003) #        mov     r0, r3
+        self.mc.write32(0xe24bd00c) #        sub     sp, fp, #12     ; 0xc
+        self.mc.write32(0xe89da800) #        ldm     sp, {fp, sp, pc}
+
+    def gen_preamble(self):
+        self.mc.write32(0xe1a0c00d) # mov     ip, sp
+        self.mc.write32(0xe92dd800) #push    {fp, ip, lr, pc}
+        self.mc.write32(0xe24cb004) # sub     fp, ip, #4      ; 0x4
+        self.mc.write32(0xe24dd008) #sub     sp, sp, #8      ; 0x8
+        self.mc.write32(0xe50b0014) # str     r0, [fp, #-20]
+
+    def gen_load_int(self, reg, value):
+        self.mc.MOV_ri(reg, (value & 0xFF))
+
+        for offset in range(8, 25, 8):
+            self.mc.MOV_ri(r.ip, (value >> offset) & 0xFF)
+            self.mc.ORR_rr(reg, reg, r.ip, offset)

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py	Tue Oct  5 21:33:10 2010
@@ -0,0 +1,43 @@
+from pypy.jit.backend.arm.assembler import AssemblerARM
+from pypy.jit.backend.llsupport.llmodel import AbstractLLCPU
+from pypy.rpython.llinterp import LLInterpreter
+from pypy.rpython.lltypesystem import lltype, rffi
+
+
+class ArmCPU(AbstractLLCPU):
+
+    BOOTSTRAP_TP = lltype.FuncType([], lltype.Signed)
+    supports_floats = False
+
+    def __init__(self, rtyper, stats, opts=None, translate_support_code=False,
+                 gcdescr=None):
+        AbstractLLCPU.__init__(self, rtyper, stats, opts,
+                               translate_support_code, gcdescr)
+        self.assembler = AssemblerARM(self)
+
+    def compile_loop(self, inputargs, operations, looptoken):
+        self.assembler.assemble_loop(inputargs, operations, looptoken)
+
+    def set_future_value_int(self, index, intvalue):
+        self.assembler.fail_boxes_int.setitem(index, intvalue)
+
+    def get_latest_value_int(self, index):
+        return self.assembler.fail_boxes_int.getitem(index)
+
+    def execute_token(self, executable_token):
+        addr = self.assembler.mc.baseaddr()#executable_token._arm_bootstrap_code
+        assert addr % 8 == 0
+        func = rffi.cast(lltype.Ptr(self.BOOTSTRAP_TP), addr)
+        fail_index = self._execute_call(func)
+        return self.get_fail_descr_from_number(fail_index)
+
+    def _execute_call(self, func):
+        #prev_interpreter = LLInterpreter.current_interpreter
+        #LLInterpreter.current_interpreter = self.debug_ll_interpreter
+        res = 0
+        #try:
+        res = func()
+        #finally:
+        #    LLInterpreter.current_interpreter = prev_interpreter
+        return res
+

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_runner.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_runner.py	Tue Oct  5 21:33:10 2010
@@ -0,0 +1,13 @@
+from pypy.jit.backend.arm.runner import ArmCPU
+from pypy.jit.backend.test.runner_test import LLtypeBackendTest
+
+class FakeStats(object):
+    pass
+
+class TestARM(LLtypeBackendTest):
+
+    # for the individual tests see
+    # ====> ../../test/runner_test.py
+
+    def setup_method(self, meth):
+        self.cpu = ArmCPU(rtyper=None, stats=FakeStats())



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