[pypy-svn] r77655 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test

david at codespeak.net david at codespeak.net
Wed Oct 6 17:00:31 CEST 2010


Author: david
Date: Wed Oct  6 17:00:29 2010
New Revision: 77655

Modified:
   pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
Log:
Encode and use PUSH instr to push a set of registers to the stack

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py	Wed Oct  6 17:00:29 2010
@@ -17,7 +17,7 @@
     def assemble_loop(self, inputargs, operations, looptoken):
         assert len(inputargs) == 1
         reg = 0
-        self.gen_preamble()
+        self.gen_func_prolog()
         addr = self.fail_boxes_int.get_addr_for_num(0)
         self.gen_load_int(r.r3, addr)
         self.mc.LDR_ri(r.r2, r.r3)
@@ -28,19 +28,18 @@
                 n = self.cpu.get_fail_descr_number(op.getdescr())
                 self.mc.MOV_ri(r.r0, n)
                 self.mc.STR_ri(r.r1, r.r3)
-                self.gen_out()
+                self.gen_func_epilog()
 
-    def gen_out(self):
+    def gen_func_epilog(self):
         self.mc.write32(0xe50b3010) #        str     r3, [fp, #-16]
         self.mc.write32(0xe51b3010) #        ldr     r3, [fp, #-16]
         #self.mc.write32(0xe1a00003) #        mov     r0, r3
         self.mc.write32(0xe24bd00c) #        sub     sp, fp, #12     ; 0xc
         self.mc.write32(0xe89da800) #        ldm     sp, {fp, sp, pc}
 
-    def gen_preamble(self):
+    def gen_func_prolog(self):
         self.mc.MOV_rr(r.ip, r.sp)
-        #self.mc.write32(0xe1a0c00d) # mov     ip, sp
-        self.mc.write32(0xe92dd800) #push    {fp, ip, lr, pc}
+        self.mc.PUSH([r.fp, r.ip, r.lr, r.pc])
         self.mc.write32(0xe24cb004) # sub     fp, ip, #4      ; 0x4
         self.mc.write32(0xe24dd008) #sub     sp, sp, #8      ; 0x8
         self.mc.write32(0xe50b0014) # str     r0, [fp, #-20]

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	Wed Oct  6 17:00:29 2010
@@ -70,6 +70,12 @@
                     | (shifttype & 0x3) << 5
                     | (rm & 0xFF))
 
+    def PUSH(self, regs, cond=cond.AL):
+        instr = cond << 28 | 0x92D << 16
+        for reg in regs:
+            instr |= 0x1 << reg
+        self.write32(instr)
+
     def write32(self, word):
         self.writechar(chr(word & 0xFF))
         self.writechar(chr((word >> 8) & 0xFF))

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py	Wed Oct  6 17:00:29 2010
@@ -1,5 +1,6 @@
 r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 = range(16)
 # aliases for registers
+fp = 11
 ip = 12
 sp = 13
 lr = 14

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py	Wed Oct  6 17:00:29 2010
@@ -9,28 +9,28 @@
         self.a = AssemblerARM(None)
 
     def test_load_small_int_to_reg(self):
-        self.a.gen_preamble()
+        self.a.gen_func_prolog()
         self.a.gen_load_int(r.r0, 123)
-        self.a.gen_out()
+        self.a.gen_func_epilog()
         assert run_asm(self.a) == 123
 
     def test_load_medium_int_to_reg(self):
-        self.a.gen_preamble()
+        self.a.gen_func_prolog()
         self.a.gen_load_int(r.r0, 0xBBD7)
-        self.a.gen_out()
+        self.a.gen_func_epilog()
         assert run_asm(self.a) == 48087
 
     def test_load_int_to_reg(self):
-        self.a.gen_preamble()
+        self.a.gen_func_prolog()
         self.a.gen_load_int(r.r0, 0xFFFFFF85)
-        self.a.gen_out()
+        self.a.gen_func_epilog()
         assert run_asm(self.a) == -123
 
 
     def test_or(self):
-        self.a.gen_preamble()
+        self.a.gen_func_prolog()
         self.a.mc.MOV_ri(r.r1, 8)
         self.a.mc.MOV_ri(r.r2, 8)
         self.a.mc.ORR_rr(r.r0, r.r1, r.r2, 4)
-        self.a.gen_out()
+        self.a.gen_func_epilog()
         assert run_asm(self.a) == 0x88

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	Wed Oct  6 17:00:29 2010
@@ -18,32 +18,32 @@
 
     def test_ldr(self):
         self.cb.LDR_ri(r.r0, r.r1)
-        self.assert_equal("LDR r0, [r1]")
+        self.assert_equal('LDR r0, [r1]')
 
     def test_add_ri(self):
         self.cb.ADD_ri(r.r0, r.r1, 1)
-        self.assert_equal("ADD r0, r1, #1")
+        self.assert_equal('ADD r0, r1, #1')
 
     def test_mov_rr(self):
         self.cb.MOV_rr(r.r7, r.r12)
-        self.assert_equal("MOV r7, r12")
+        self.assert_equal('MOV r7, r12')
 
     def test_mov_ri(self):
         self.cb.MOV_ri(r.r9, 123)
-        self.assert_equal("MOV r9, #123")
+        self.assert_equal('MOV r9, #123')
 
     def test_mov_ri2(self):
         self.cb.MOV_ri(r.r9, 255)
-        self.assert_equal("MOV r9, #255")
+        self.assert_equal('MOV r9, #255')
 
     def test_mov_ri_max(self):
-        py.test.skip("Check the actual largest thing")
+        py.test.skip('Check the actual largest thing')
         self.cb.MOV_ri(r.r9, 0xFFF)
-        self.assert_equal("MOV r9, #4095")
+        self.assert_equal('MOV r9, #4095')
 
     def test_str_ri(self):
         self.cb.STR_ri(r.r9, r.r14)
-        self.assert_equal("STR r9, [r14]")
+        self.assert_equal('STR r9, [r14]')
 
     def test_asr_ri(self):
         self.cb.ASR_ri(r.r7, r.r5, 24)
@@ -57,6 +57,18 @@
         self.cb.ORR_rr(r.r0, r.r7,r.r12, 8)
         self.assert_equal('ORR r0, r7, r12, lsl #8')
 
+    def test_push_one_reg(self):
+        self.cb.PUSH([r.r1])
+        self.assert_equal('PUSH {r1}')
+
+    def test_push_multiple(self):
+        self.cb.PUSH([r.r3, r.r1, r.r6, r.r8, r.sp, r.pc])
+        self.assert_equal('PUSH {r3, r1, r6, r8, sp, pc}')
+
+    def test_push_multiple2(self):
+        self.cb.PUSH([r.fp, r.ip, r.lr, r.pc])
+        self.assert_equal('PUSH {fp, ip, lr, pc}')
+
     def assert_equal(self, asm):
         assert self.cb.hexdump() == assemble(asm)
 



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