[pypy-svn] r77656 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test

[david at codespeak.net]

Author: david
Date: Wed Oct  6 17:36:09 2010
New Revision: 77656

Modified:
   pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
Log:
Encoding for SUB instr

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py	Wed Oct  6 17:36:09 2010
@@ -34,14 +34,14 @@
         self.mc.write32(0xe50b3010) #        str     r3, [fp, #-16]
         self.mc.write32(0xe51b3010) #        ldr     r3, [fp, #-16]
         #self.mc.write32(0xe1a00003) #        mov     r0, r3
-        self.mc.write32(0xe24bd00c) #        sub     sp, fp, #12     ; 0xc
+        self.mc.SUB_ri(r.sp, r.fp, 12)
         self.mc.write32(0xe89da800) #        ldm     sp, {fp, sp, pc}
 
     def gen_func_prolog(self):
         self.mc.MOV_rr(r.ip, r.sp)
         self.mc.PUSH([r.fp, r.ip, r.lr, r.pc])
-        self.mc.write32(0xe24cb004) # sub     fp, ip, #4      ; 0x4
-        self.mc.write32(0xe24dd008) #sub     sp, sp, #8      ; 0x8
+        self.mc.SUB_ri(r.fp, r.ip, 4)
+        self.mc.SUB_ri(r.sp, r.sp, 8)
         self.mc.write32(0xe50b0014) # str     r0, [fp, #-20]
 
     def gen_load_int(self, reg, value):

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	Wed Oct  6 17:36:09 2010
@@ -25,6 +25,16 @@
                         | (rn & 0xF) << 16
                         | (rt & 0xF) << 12
                         | (imm & 0xFFF))
+
+    def SUB_ri(self, rd, rn, imm=0, cond=cond.AL, s=0):
+        self.write32(cond << 28
+                        | 9 << 22
+                        | (s & 0x1) << 20
+                        | (rn & 0xF) << 16
+                        | (rd & 0xF) << 12
+                        | (imm & 0xFFF))
+
+
     def MOV_rr(self, rd, rm, cond=cond.AL, s=0):
         self.write32(cond << 28
                     | 0xD << 21

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py	Wed Oct  6 17:36:09 2010
@@ -34,3 +34,10 @@
         self.a.mc.ORR_rr(r.r0, r.r1, r.r2, 4)
         self.a.gen_func_epilog()
         assert run_asm(self.a) == 0x88
+
+    def test_sub(self):
+        self.a.gen_func_prolog()
+        self.a.gen_load_int(r.r1, 123456)
+        self.a.mc.SUB_ri(r.r0, r.r1, 123)
+        self.a.gen_func_epilog()
+        assert run_asm(self.a) == 123333

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	Wed Oct  6 17:36:09 2010
@@ -69,6 +69,15 @@
         self.cb.PUSH([r.fp, r.ip, r.lr, r.pc])
         self.assert_equal('PUSH {fp, ip, lr, pc}')
 
+    def test_sub_ri(self):
+        self.cb.SUB_ri(r.r2, r.r4, 123)
+        self.assert_equal('SUB r2, r4, #123')
+
+    def test_sub_ri2(self):
+        py.test.skip('XXX check the actual largest value')
+        self.cb.SUB_ri(r.r3, r.r7, 0xFFF)
+        self.assert_equal('SUB r3, r7, #4095')
+
     def assert_equal(self, asm):
         assert self.cb.hexdump() == assemble(asm)