[pypy-svn] r77754 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test

david at codespeak.net david at codespeak.net
Sun Oct 10 12:47:52 CEST 2010


Author: david
Date: Sun Oct 10 12:47:51 2010
New Revision: 77754

Modified:
   pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/support.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
Log:
Implemtent INT_LE and GUARD_TRUE operations and make test_compile_loop pass


Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py	Sun Oct 10 12:47:51 2010
@@ -1,5 +1,6 @@
 from pypy.jit.backend.arm.codebuilder import ARMv7Builder
 from pypy.jit.backend.arm import registers as r
+from pypy.jit.backend.arm import conditions as c
 #from pypy.jit.backend.arm.regalloc import RegAlloc, ARMRegisterManager
 from pypy.jit.metainterp.resoperation import rop
 from pypy.rpython.lltypesystem import lltype
@@ -20,25 +21,43 @@
         self.gen_func_prolog()
         addr = self.fail_boxes_int.get_addr_for_num(0)
         self.gen_load_int(r.r3, addr)
-        self.mc.LDR_ri(r.r2, r.r3)
+        self.mc.LDR_ri(r.r1, r.r3)
+        loop_head=self.mc.curraddr()
+        fcond=c.AL
         for op in operations:
-            if op.getopnum() == rop.INT_ADD:
-                self.mc.ADD_ri(r.r1, r.r2, op.getarg(1).getint())
-            elif op.getopnum() == rop.FINISH:
+            opnum = op.getopnum()
+            if opnum == rop.INT_ADD:
+                self.mc.ADD_ri(r.r1, r.r1, op.getarg(1).getint())
+            elif opnum == rop.INT_LE:
+                self.mc.CMP(r.r1, op.getarg(1).getint())
+                fcond = c.GT
+            elif opnum == rop.GUARD_TRUE:
+                n = self.cpu.get_fail_descr_number(op.getdescr())
+                self.mc.MOV_ri(r.r0, n, cond=fcond)
+                self.mc.STR_ri(r.r1, r.r3, cond=fcond)
+                self.gen_func_epilog(cond=fcond)
+                fcond = c.AL
+            elif opnum == rop.JUMP:
+                self.gen_load_int(r.r7, loop_head)
+                self.mc.MOV_rr(r.pc, r.r7)
+            elif opnum == rop.FINISH:
                 n = self.cpu.get_fail_descr_number(op.getdescr())
                 self.mc.MOV_ri(r.r0, n)
                 self.mc.STR_ri(r.r1, r.r3)
-                self.gen_func_epilog()
+            else:
+                raise ValueError("Unknown op %r" % op)
+        self.gen_func_epilog()
 
-    def gen_func_epilog(self):
-        self.mc.LDM(r.sp, r.callee_restored_registers)
+    def gen_func_epilog(self,cond=c.AL):
+        self.mc.LDM(r.sp, r.callee_restored_registers, cond=cond)
 
     def gen_func_prolog(self):
         self.mc.PUSH(r.callee_saved_registers)
 
-    def gen_load_int(self, reg, value):
-        self.mc.MOV_ri(reg, (value & 0xFF))
+    def gen_load_int(self, reg, value, cond=c.AL):
+        assert reg != r.ip, 'ip is used to load int'
+        self.mc.MOV_ri(reg, (value & 0xFF), cond=cond)
 
         for offset in range(8, 25, 8):
-            self.mc.MOV_ri(r.ip, (value >> offset) & 0xFF)
-            self.mc.ORR_rr(reg, reg, r.ip, offset)
+            self.mc.MOV_ri(r.ip, (value >> offset) & 0xFF, cond=cond)
+            self.mc.ORR_rr(reg, reg, r.ip, offset, cond=cond)

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	Sun Oct 10 12:47:51 2010
@@ -8,13 +8,6 @@
         self._data = alloc(1024)
         self._pos = 0
 
-    def _encode_imm(self, imm):
-        u = 1
-        if imm < 0:
-            u = 0
-            imm = -imm
-        return u, imm
-
     def LDR_ri(self, rt, rn, imm=0, cond=cond.AL):
         #  XXX W and P bits are not encoded yet
         p = 1
@@ -109,11 +102,27 @@
         instr = self._encode_reg_list(instr, regs)
         self.write32(instr)
 
+    def CMP(self, rn, imm, cond=cond.AL):
+        if 0 <= imm <= 255:
+            self.write32(cond << 28
+                        | 0x35 << 20
+                        | (rn & 0xFF) <<  16
+                        | (imm & 0xFFF))
+        else:
+            raise NotImplentedError
+
     def _encode_reg_list(self, instr, regs):
         for reg in regs:
             instr |= 0x1 << reg
         return instr
 
+    def _encode_imm(self, imm):
+        u = 1
+        if imm < 0:
+            u = 0
+            imm = -imm
+        return u, imm
+
     def write32(self, word):
         self.writechar(chr(word & 0xFF))
         self.writechar(chr((word >> 8) & 0xFF))
@@ -127,4 +136,7 @@
     def baseaddr(self):
         return rffi.cast(lltype.Signed, self._data)
 
+    def curraddr(self):
+        return self.baseaddr() + self._pos
+
 

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/support.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/support.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/support.py	Sun Oct 10 12:47:51 2010
@@ -1,4 +1,5 @@
 import os
+import py
 
 from pypy.rpython.lltypesystem import lltype, rffi
 
@@ -15,7 +16,6 @@
     return func()
 
 def skip_unless_arm():
-    import py
     check_skip(os.uname()[4])
 
 def requires_arm_as():

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py	Sun Oct 10 12:47:51 2010
@@ -1,4 +1,5 @@
 from pypy.jit.backend.arm import registers as r
+from pypy.jit.backend.arm import conditions as c
 from pypy.jit.backend.arm.assembler import AssemblerARM
 from pypy.jit.backend.arm.test.support import skip_unless_arm, run_asm
 
@@ -41,3 +42,47 @@
         self.a.mc.SUB_ri(r.r0, r.r1, 123)
         self.a.gen_func_epilog()
         assert run_asm(self.a) == 123333
+
+    def test_int_le(self):
+        self.a.gen_func_prolog()
+        self.a.gen_load_int(r.r1, 22)
+        self.a.mc.CMP(r.r1, 123)
+        self.a.mc.MOV_ri(r.r0, 1, c.LE)
+        self.a.mc.MOV_ri(r.r0, 0, c.GT)
+        self.a.gen_func_epilog()
+        assert run_asm(self.a) == 1
+
+    def test_int_le_false(self):
+        self.a.gen_func_prolog()
+        self.a.gen_load_int(r.r1, 2222)
+        self.a.mc.CMP(r.r1, 123)
+        self.a.mc.MOV_ri(r.r0, 1, c.LE)
+        self.a.mc.MOV_ri(r.r0, 0, c.GT)
+        self.a.gen_func_epilog()
+        assert run_asm(self.a) == 0
+
+    def test_simple_jump(self):
+        self.a.gen_func_prolog()
+        self.a.mc.MOV_ri(r.r1, 1)
+        loop_head = self.a.mc.curraddr()
+        self.a.mc.CMP(r.r1, 0) # z=0, z=1
+        self.a.mc.MOV_ri(r.r1, 0, cond=c.NE)
+        self.a.mc.MOV_ri(r.r1, 7, cond=c.EQ)
+        self.a.gen_load_int(r.r4, loop_head, cond=c.NE)
+        self.a.mc.MOV_rr(r.pc, r.r4, cond=c.NE)
+        self.a.mc.MOV_rr(r.r0, r.r1)
+        self.a.gen_func_epilog()
+        assert run_asm(self.a) == 7
+
+    def test_jump(self):
+        self.a.gen_func_prolog()
+        self.a.mc.MOV_ri(r.r1, 1)
+        loop_head = self.a.mc.curraddr()
+        self.a.mc.ADD_ri(r.r1, r.r1, 1)
+        self.a.mc.CMP(r.r1, 9)
+        self.a.gen_load_int(r.r4, loop_head, cond=c.NE)
+        self.a.mc.MOV_rr(r.pc, r.r4, cond=c.NE)
+        self.a.mc.MOV_rr(r.r0, r.r1)
+        self.a.gen_func_epilog()
+        assert run_asm(self.a) == 9
+

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	Sun Oct 10 12:47:51 2010
@@ -106,6 +106,10 @@
         self.cb.SUB_ri(r.r3, r.r7, 0xFFF)
         self.assert_equal('SUB r3, r7, #4095')
 
+    def test_cmp_ri(self):
+        self.cb.CMP(r.r3, 123)
+        self.assert_equal('CMP r3, #123')
+
     def assert_equal(self, asm):
         assert self.cb.hexdump() == assemble(asm)
 



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