[pypy-svn] r77926 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test

david at codespeak.net david at codespeak.net
Thu Oct 14 14:45:47 CEST 2010


Author: david
Date: Thu Oct 14 14:45:45 2010
New Revision: 77926

Added:
   pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py
Modified:
   pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
   pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
Log:
Refactor parts of the codebuilder, build load and store instructions from a table


Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py	Thu Oct 14 14:45:45 2010
@@ -1,6 +1,7 @@
 import conditions as cond
 from pypy.rlib.rmmap import alloc
 from pypy.rpython.lltypesystem import lltype, rffi
+from pypy.jit.backend.arm.instruction_builder import define_instructions
 
 class ARMv7Builder(object):
 
@@ -8,21 +9,6 @@
         self._data = alloc(1024)
         self._pos = 0
 
-    def LDR_ri(self, rt, rn, imm=0, cond=cond.AL):
-        #  XXX W and P bits are not encoded yet
-        p = 1
-        w = 0
-        u, imm = self._encode_imm(imm)
-        self.write32(cond << 28
-                        | 0x1 << 26
-                        | (p & 0x1) << 24
-                        | (u & 0x1) << 23
-                        | (w & 0x1) << 21
-                        | 0x1 << 20
-                        | (rn & 0xF) << 16
-                        | (rt & 0xF) << 12
-                        | (imm & 0xFFF))
-
     def ADD_ri(self, rt, rn, imm, cond=cond.AL):
         # XXX S bit
         self.write32(cond << 28
@@ -58,20 +44,6 @@
                     | (rt & 0xF) << 12
                     | (imm & 0xFFF))
 
-    def STR_ri(self, rt, rn, imm=0, cond=cond.AL):
-        #  XXX W and P bits are not encoded yet
-        p = 1
-        w = 0
-        u, imm = self._encode_imm(imm)
-        self.write32(cond << 28
-                    | 0x1 << 26
-                    | (p & 0x1) << 24
-                    | (u & 0x1) << 23
-                    | (w & 0x1) << 21
-                    | (rn & 0xF) << 16
-                    | (rt & 0xF) << 12
-                    | (imm & 0xFFF))
-
     def ASR_ri(self, rd, rm, imm=0, cond=cond.AL, s=0):
         self.write32(cond << 28
                     | 0xD << 21
@@ -139,4 +111,4 @@
     def curraddr(self):
         return self.baseaddr() + self._pos
 
-
+define_instructions(ARMv7Builder)

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/instruction_builder.py	Thu Oct 14 14:45:45 2010
@@ -0,0 +1,43 @@
+from pypy.jit.backend.arm import conditions as cond
+from pypy.jit.backend.arm import instructions
+
+def define_load_store_func(target, name, table):
+    #  XXX W and P bits are not encoded yet
+    n = (0x1 << 26
+        | (table['A'] & 0x1) << 25
+        | (table['op1'] & 0x1F) << 20
+        | (table['B'] & 0x1) << 4)
+    if table['imm']:
+        def f(self, rt, rn, imm=0, cond=cond.AL):
+            p = 1
+            w = 0
+            u, imm = self._encode_imm(imm)
+            self.write32(n
+                    | cond << 28
+                    | (p & 0x1) <<  24
+                    | (u & 0x1) << 23
+                    | (w & 0x1) << 21
+                    | (rn & 0xFF) << 16
+                    | (rt & 0xFF) << 12
+                    | (imm & 0xFFF))
+    else:
+        def f(self, rt, rn, rm, imm=0, cond=cond.AL, s=0, shifttype=0):
+            p = 1
+            w = 0
+            u, imm = self._encode_imm(imm)
+            self.write32(n
+                        | cond << 28
+                        | (p & 0x1) <<  24
+                        | (u & 0x1) << 23
+                        | (w & 0x1) << 21
+                        | (rn & 0xFF) << 16
+                        | (rt & 0xFF) << 12
+                        | (imm & 0x1F) << 7
+                        | (shifttype & 0x3) << 5
+                        | (rm & 0xFF))
+
+    setattr(target, name, f)
+
+def define_instructions(target):
+    for key, val in instructions.load_store.iteritems():
+        define_load_store_func(target, key, val)

Added: pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py
==============================================================================
--- (empty file)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py	Thu Oct 14 14:45:45 2010
@@ -0,0 +1,12 @@
+# XXX ensure b value is as expected
+# XXX add not assertions for op1
+load_store = {
+    'STR_ri': {'A':0, 'op1': 0x0, 'B': 0, 'imm': True},
+    'STR_rr': {'A':1, 'op1': 0x0, 'B': 0, 'imm': False},
+    'LDR_ri': {'A':0, 'op1': 0x1, 'B': 0, 'imm': True},
+    'LDR_rr': {'A':1, 'op1': 0x1, 'B': 0, 'imm': False},
+    'STRB_ri': {'A':0, 'op1': 0x4, 'B': 0, 'imm': True},
+    'STRB_rr': {'A':1, 'op1': 0x4, 'B': 0, 'imm': False},
+    'LDRB_ri': {'A':0, 'op1': 0x5, 'B': 0, 'imm': True},
+    'LDRB_rr': {'A':1, 'op1': 0x5, 'B': 0, 'imm': False},
+}

Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	(original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py	Thu Oct 14 14:45:45 2010
@@ -1,5 +1,6 @@
 from pypy.jit.backend.arm import registers as r
 from pypy.jit.backend.arm import codebuilder
+from pypy.jit.backend.arm import instructions
 from pypy.jit.backend.arm.test.support import requires_arm_as
 from gen import assemble
 import py
@@ -15,8 +16,11 @@
 
     def hexdump(self):
         return ''.join(self.buffer)
+class ASMTest(object):
+    def assert_equal(self, asm):
+        assert self.cb.hexdump() == assemble(asm)
 
-class TestInstrCodeBuilder(object):
+class TestInstrCodeBuilder(ASMTest):
     def setup_method(self, ffuu_method):
         self.cb = CodeBuilder()
 
@@ -110,6 +114,31 @@
         self.cb.CMP(r.r3, 123)
         self.assert_equal('CMP r3, #123')
 
-    def assert_equal(self, asm):
-        assert self.cb.hexdump() == assemble(asm)
 
+class TestInstrCodeBuilderForGeneratedInstr(ASMTest):
+    def setup_method(self, ffuu_method):
+        self.cb = CodeBuilder()
+
+def build_tests():
+    for key, value in instructions.load_store.iteritems():
+        if value['imm']:
+            f = gen_test_imm_func
+        else:
+            f = gen_test_reg_func
+        test = f(key, value)
+    setattr(TestInstrCodeBuilderForGeneratedInstr, 'test_%s' % key, test)
+
+def gen_test_imm_func(name, table):
+    def f(self):
+        func = getattr(self.cb, name)
+        func(r.r3, r.r7, 23)
+        self.assert_equal('%s r3, [r7, #23]' % name[:name.index('_')])
+    return f
+
+def gen_test_reg_func(name, table):
+    def f(self):
+        func = getattr(self.cb, name)
+        func(r.r3, r.r7, r.r12)
+        self.assert_equal('%s r3, [r7, r12]' % name[:name.index('_')])
+    return f
+build_tests()



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