[pypy-svn] pypy arm-backed-float: simplify the code a bit, here we now values are in register

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: arm-backed-float
Changeset: r43092:b083504273b0
Date: 2011-04-01 17:23 +0200
http://bitbucket.org/pypy/pypy/changeset/b083504273b0/

Log:	simplify the code a bit, here we now values are in register

diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -491,11 +491,9 @@
 
         if scale.value == 3:
             assert value_loc.is_vfp_reg()
-            if scale_loc.is_reg():
-                self.mc.ADD_rr(r.ip.value, base_loc.value, scale_loc.value)
-                base_loc = r.ip
-                scale_loc = locations.imm(0)
-            self.mc.VSTR(value_loc.value, base_loc.value, scale_loc.value, cond=fcond)
+            assert scale_loc.is_reg()
+            self.mc.ADD_rr(r.ip.value, base_loc.value, scale_loc.value)
+            self.mc.VSTR(value_loc.value, r.ip.value, cond=fcond)
         elif scale.value == 2:
             self.mc.STR_rr(value_loc.value, base_loc.value, scale_loc.value, cond=fcond)
         elif scale.value == 1:
@@ -521,11 +519,9 @@
 
         if scale.value == 3:
             assert res.is_vfp_reg()
-            if scale_loc.is_reg():
-                self.mc.ADD_rr(r.ip.value, base_loc.value, scale_loc.value)
-                base_loc = r.ip
-                scale_loc = locations.imm(0)
-            self.mc.VLDR(res.value, base_loc.value, scale_loc.value, cond=fcond)
+            assert scale_loc.is_reg()
+            self.mc.ADD_rr(r.ip.value, base_loc.value, scale_loc.value)
+            self.mc.VLDR(res.value, r.ip.value, cond=fcond)
         elif scale.value == 2:
             self.mc.LDR_rr(res.value, base_loc.value, scale_loc.value, cond=fcond)
         elif scale.value == 1: