[pypy-svn] pypy arm-backed-float: register allocation related fixes due to operation merges
bivab
commits-noreply at bitbucket.org
Tue Apr 19 14:41:03 CEST 2011
Author: David Schneider <david.schneider at picle.org>
Branch: arm-backed-float
Changeset: r43481:cf45d0813fb5
Date: 2011-04-19 14:11 +0200
http://bitbucket.org/pypy/pypy/changeset/cf45d0813fb5/
Log: register allocation related fixes due to operation merges
diff --git a/pypy/jit/backend/arm/assembler.py b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -680,7 +680,6 @@
self.mc.gen_load_int(r.ip.value, value.getint())
self.mc.VLDR(loc.value, r.ip.value)
- # XXX needs float support
def regalloc_mov(self, prev_loc, loc, cond=c.AL):
if prev_loc.is_imm():
if loc.is_reg():
diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -296,7 +296,7 @@
else:
self.rm._sync_var(v)
- def prepare_op_int_add(self, op, fcond):
+ def _prepare_op_int_add(self, op, fcond):
boxes = list(op.getarglist())
a0, a1 = boxes
imm_a0 = _check_imm_arg(a0)
@@ -314,10 +314,15 @@
boxes.append(box)
l1, box = self._ensure_value_is_boxed(a1, [box])
boxes.append(box)
+ return [l0, l1], boxes
+
+ def prepare_op_int_add(self, op, fcond):
+ locs, boxes = self._prepare_op_int_add(op, fcond)
+ self.possibly_free_vars(boxes)
res = self.force_allocate_reg(op.result)
- return [l0, l1, res]
+ return locs + [res]
- def prepare_op_int_sub(self, op, fcond):
+ def _prepare_op_int_sub(self, op, fcond):
boxes = list(op.getarglist())
a0, a1 = boxes
imm_a0 = _check_imm_arg(a0)
@@ -335,8 +340,13 @@
boxes.append(box)
l1, box = self._ensure_value_is_boxed(a1, boxes)
boxes.append(box)
+ return [l0, l1], boxes
+
+ def prepare_op_int_sub(self, op, fcond):
+ locs, boxes = self._prepare_op_int_sub(op, fcond)
+ self.possibly_free_vars(boxes)
res = self.force_allocate_reg(op.result)
- return [l0, l1, res]
+ return locs + [res]
def prepare_op_int_mul(self, op, fcond):
boxes = list(op.getarglist())
@@ -372,15 +382,21 @@
def prepare_guard_int_add_ovf(self, op, guard, fcond):
- boxes = self.prepare_op_int_add(op, fcond)
- locs = self._prepare_guard(guard, boxes)
+ locs, boxes = self._prepare_op_int_add(op, fcond)
+ res = self.force_allocate_reg(op.result)
+ locs.append(res)
+ locs = self._prepare_guard(guard, locs)
+ self.possibly_free_vars(boxes)
self.possibly_free_vars_for_op(op)
self.possibly_free_vars(guard.getfailargs())
return locs
def prepare_guard_int_sub_ovf(self, op, guard, fcond):
- boxes = self.prepare_op_int_sub(op, fcond)
- locs = self._prepare_guard(guard, boxes)
+ locs, boxes = self._prepare_op_int_sub(op, fcond)
+ res = self.force_allocate_reg(op.result)
+ locs.append(res)
+ locs = self._prepare_guard(guard, locs)
+ self.possibly_free_vars(boxes)
self.possibly_free_vars_for_op(op)
self.possibly_free_vars(guard.getfailargs())
return locs
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