[pypy-commit] pypy ppc-jit-backend: Added initial translation of INT_MUL.

hager noreply at buildbot.pypy.org
Fri Aug 12 13:27:08 CEST 2011


Author: hager <sven.hager at uni-duesseldorf.de>
Branch: ppc-jit-backend
Changeset: r46468:38f60e97182c
Date: 2011-08-12 13:29 +0200
http://bitbucket.org/pypy/pypy/changeset/38f60e97182c/

Log:	Added initial translation of INT_MUL. Needs some refactorings in the
	future.

diff --git a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
--- a/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/ppc_assembler.py
@@ -904,6 +904,8 @@
             self.emit_int_add(trace_op, cpu)
         elif opnum == rop.INT_SUB:
             self.emit_int_sub(trace_op, cpu)
+        elif opnum == rop.INT_MUL:
+            self.emit_int_mul(trace_op, cpu)
         elif opnum == rop.FINISH:
             self.emit_finish(trace_op, cpu)
         elif opnum == rop.INT_LE:
@@ -957,6 +959,25 @@
         cpu.reg_map[result] = cpu.next_free_register
         cpu.next_free_register += 1
 
+    def emit_int_mul(self, op, cpu):
+        # XXX need to care about factors whose product needs 64 bit
+        arg0 = op.getarg(0)
+        arg1 = op.getarg(1)
+        if isinstance(arg0, BoxInt):
+            reg0 = cpu.reg_map[arg0]
+        else:
+            reg0 = cpu.get_next_register()
+            self.load_word(reg0, arg0.value)
+        if isinstance(arg1, BoxInt):
+            reg1 = cpu.reg_map[arg1]
+        else:
+            reg1 = cpu.get_next_register()
+            self.load_word(reg1, arg1.value)
+        self.mullw(cpu.next_free_register, reg0, reg1)
+        result = op.result
+        cpu.reg_map[result] = cpu.next_free_register
+        cpu.next_free_register += 1
+
     def emit_int_eq(self, op, cpu):
         arg0 = op.getarg(0)
         arg1 = op.getarg(1)


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