[pypy-commit] pypy arm-backend-2: make the save_exc parameter non-optional
bivab
noreply at buildbot.pypy.org
Thu Dec 29 09:57:18 CET 2011
Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r50938:18234110368e
Date: 2011-12-13 15:53 +0100
http://bitbucket.org/pypy/pypy/changeset/18234110368e/
Log: make the save_exc parameter non-optional
diff --git a/pypy/jit/backend/arm/assembler.py b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -155,7 +155,7 @@
self.releasegil_addr = rffi.cast(lltype.Signed, releasegil_func)
self.reacqgil_addr = rffi.cast(lltype.Signed, reacqgil_func)
- def _gen_leave_jitted_hook_code(self, save_exc=False):
+ def _gen_leave_jitted_hook_code(self, save_exc):
mc = ARMv7Builder()
# XXX add a check if cpu supports floats
with saved_registers(mc, r.caller_resp + [r.ip], r.caller_vfp_resp):
@@ -428,12 +428,14 @@
encode32(mem, j+1, n)
return memaddr
- def _gen_path_to_exit_path(self, descr, args, arglocs, fcond=c.AL, save_exc=False):
+ def _gen_path_to_exit_path(self, descr, args, arglocs, save_exc, fcond=c.AL):
+ assert isinstance(save_exc, bool)
memaddr = self.gen_descr_encoding(descr, args, arglocs)
- self.gen_exit_code(self.mc, memaddr, fcond, save_exc)
+ self.gen_exit_code(self.mc, memaddr, save_exc, fcond)
return memaddr
- def gen_exit_code(self, mc, memaddr, fcond=c.AL, save_exc=False):
+ def gen_exit_code(self, mc, memaddr, save_exc, fcond=c.AL):
+ assert isinstance(save_exc, bool)
self.mc.gen_load_int(r.ip.value, memaddr)
#mc.LDR_ri(r.ip.value, r.pc.value, imm=WORD)
if save_exc:
@@ -888,7 +890,7 @@
# regalloc support
def load(self, loc, value):
- assert (loc.is_reg() and value.is_imm()
+ assert (loc.is_reg() and value.is_imm()
or loc.is_vfp_reg() and value.is_imm_float())
if value.is_imm():
self.mc.gen_load_int(loc.value, value.getint())
diff --git a/pypy/jit/backend/arm/helper/assembler.py b/pypy/jit/backend/arm/helper/assembler.py
--- a/pypy/jit/backend/arm/helper/assembler.py
+++ b/pypy/jit/backend/arm/helper/assembler.py
@@ -29,7 +29,7 @@
guard_opnum = guard.getopnum()
if guard_opnum == rop.GUARD_FALSE:
cond = false_cond
- return self._emit_guard(guard, arglocs[1:], cond)
+ return self._emit_guard(guard, arglocs[1:], cond, save_exc=False)
f.__name__ = 'emit_guard_%s' % name
return f
@@ -92,7 +92,7 @@
cond = true_cond
if guard_opnum == rop.GUARD_FALSE:
cond = false_cond
- return self._emit_guard(guard, arglocs[2:], cond)
+ return self._emit_guard(guard, arglocs[2:], cond, save_exc=False)
f.__name__ = 'emit_guard_%s' % name
return f
@@ -137,7 +137,7 @@
guard_opnum = guard.getopnum()
if guard_opnum == rop.GUARD_FALSE:
cond = false_cond
- return self._emit_guard(guard, arglocs[2:], cond)
+ return self._emit_guard(guard, arglocs[2:], cond, save_exc=False)
f.__name__ = 'emit_guard_%s' % name
return f
diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -35,8 +35,9 @@
NO_FORCE_INDEX = -1
class GuardToken(object):
- def __init__(self, descr, failargs, faillocs, offset, fcond=c.AL,
- save_exc=False, is_invalidate=False):
+ def __init__(self, descr, failargs, faillocs, offset,
+ save_exc, fcond=c.AL, is_invalidate=False):
+ assert isinstance(save_exc, bool)
self.descr = descr
self.offset = offset
self.is_invalidate = is_invalidate
@@ -99,9 +100,9 @@
self.mc.CMP_rr(r.ip.value, res.value, shifttype=shift.ASR, imm=31, cond=fcond)
if guard.getopnum() == rop.GUARD_OVERFLOW:
- fcond = self._emit_guard(guard, failargs, c.NE)
+ fcond = self._emit_guard(guard, failargs, c.NE, save_exc=False)
elif guard.getopnum() == rop.GUARD_NO_OVERFLOW:
- fcond = self._emit_guard(guard, failargs, c.EQ)
+ fcond = self._emit_guard(guard, failargs, c.EQ, save_exc=False)
else:
assert 0
return fcond
@@ -188,7 +189,9 @@
_mixin_ = True
- def _emit_guard(self, op, arglocs, fcond, save_exc=False, is_guard_not_invalidated=False):
+ def _emit_guard(self, op, arglocs, fcond, save_exc, is_guard_not_invalidated=False):
+ assert isinstance(save_exc, bool)
+ assert isinstance(fcond, int)
descr = op.getdescr()
assert isinstance(descr, AbstractFailDescr)
@@ -209,16 +212,16 @@
failargs=op.getfailargs(),
faillocs=arglocs,
offset=pos,
- fcond=fcond,
+ save_exc=save_exc,
is_invalidate=is_guard_not_invalidated,
- save_exc=save_exc))
+ fcond=fcond))
return c.AL
def _emit_guard_overflow(self, guard, failargs, fcond):
if guard.getopnum() == rop.GUARD_OVERFLOW:
- fcond = self._emit_guard(guard, failargs, c.VS)
+ fcond = self._emit_guard(guard, failargs, c.VS, save_exc=False)
elif guard.getopnum() == rop.GUARD_NO_OVERFLOW:
- fcond = self._emit_guard(guard, failargs, c.VC)
+ fcond = self._emit_guard(guard, failargs, c.VC, save_exc=False)
else:
assert 0
return fcond
@@ -227,14 +230,14 @@
l0 = arglocs[0]
failargs = arglocs[1:]
self.mc.CMP_ri(l0.value, 0)
- fcond = self._emit_guard(op, failargs, c.NE)
+ fcond = self._emit_guard(op, failargs, c.NE, save_exc=False)
return fcond
def emit_op_guard_false(self, op, arglocs, regalloc, fcond):
l0 = arglocs[0]
failargs = arglocs[1:]
self.mc.CMP_ri(l0.value, 0)
- fcond = self._emit_guard(op, failargs, c.EQ)
+ fcond = self._emit_guard(op, failargs, c.EQ, save_exc=False)
return fcond
def emit_op_guard_value(self, op, arglocs, regalloc, fcond):
@@ -251,17 +254,17 @@
assert l1.is_vfp_reg()
self.mc.VCMP(l0.value, l1.value)
self.mc.VMRS(cond=fcond)
- fcond = self._emit_guard(op, failargs, c.EQ)
+ fcond = self._emit_guard(op, failargs, c.EQ, save_exc=False)
return fcond
emit_op_guard_nonnull = emit_op_guard_true
emit_op_guard_isnull = emit_op_guard_false
def emit_op_guard_no_overflow(self, op, arglocs, regalloc, fcond):
- return self._emit_guard(op, arglocs, c.VC)
+ return self._emit_guard(op, arglocs, c.VC, save_exc=False)
def emit_op_guard_overflow(self, op, arglocs, regalloc, fcond):
- return self._emit_guard(op, arglocs, c.VS)
+ return self._emit_guard(op, arglocs, c.VS, save_exc=False)
# from ../x86/assembler.py:1265
def emit_op_guard_class(self, op, arglocs, regalloc, fcond):
@@ -273,14 +276,14 @@
self.mc.CMP_ri(arglocs[0].value, 0)
if offset is not None:
- self._emit_guard(op, arglocs[3:], c.NE)
+ self._emit_guard(op, arglocs[3:], c.NE, save_exc=False)
else:
raise NotImplementedError
self._cmp_guard_class(op, arglocs, regalloc, fcond)
return fcond
def emit_op_guard_not_invalidated(self, op, locs, regalloc, fcond):
- return self._emit_guard(op, locs, fcond, is_guard_not_invalidated=True)
+ return self._emit_guard(op, locs, fcond, save_exc=False, is_guard_not_invalidated=True)
def _cmp_guard_class(self, op, locs, regalloc, fcond):
offset = locs[2]
@@ -295,7 +298,7 @@
raise NotImplementedError
# XXX port from x86 backend once gc support is in place
- return self._emit_guard(op, locs[3:], c.EQ)
+ return self._emit_guard(op, locs[3:], c.EQ, save_exc=False)
class OpAssembler(object):
@@ -497,7 +500,7 @@
self.mc.CMP_rr(r.ip.value, loc.value)
self._emit_guard(op, failargs, c.EQ, save_exc=True)
- self.mc.gen_load_int(loc.value, pos_exc_value.value, fcond)
+ self.mc.gen_load_int(loc.value, pos_exc_value.value)
if resloc:
self.mc.LDR_ri(resloc.value, loc.value)
self.mc.MOV_ri(r.ip.value, 0)
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