[pypy-svn] pypy arm-backend-2: fix interface for gen_load_int

bivab commits-noreply at bitbucket.org
Wed Feb 16 11:26:53 CET 2011


Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r42028:47b47250e553
Date: 2011-02-13 14:54 +0100
http://bitbucket.org/pypy/pypy/changeset/47b47250e553/

Log:	fix interface for gen_load_int

diff --git a/pypy/jit/backend/arm/assembler.py b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -17,6 +17,8 @@
 from pypy.rpython.annlowlevel import llhelper
 from pypy.rpython.lltypesystem import lltype, rffi, llmemory
 from pypy.jit.backend.arm.opassembler import ResOpAssembler
+from pypy.rlib.debug import (debug_print, debug_start, debug_stop,
+                             have_debug_prints)
 
 # XXX Move to llsupport
 from pypy.jit.backend.x86.support import values_array
@@ -229,7 +231,7 @@
         # 1 separator byte
         # 4 bytes for the faildescr
         memsize = (len(arglocs)-1)*6+5
-        datablockwrapper = MachineDataBlockWrapper(self.cpu.asmmemmgr, 
+        datablockwrapper = MachineDataBlockWrapper(self.cpu.asmmemmgr,
                                                     self.blocks)
         memaddr = datablockwrapper.malloc_aligned(memsize, alignment=WORD)
         datablockwrapper.done()
@@ -336,8 +338,15 @@
         self.mc.B_offs(loop_head)
         self._patch_sp_offset(sp_patch_location, regalloc)
 
+    def _dump(self, ops, type='loop'):
+        debug_start('jit-backend-ops')
+        debug_print(type)
+        for op in ops:
+            debug_print(op.repr())
+        debug_stop('jit-backend-ops')
     # cpu interface
     def assemble_loop(self, inputargs, operations, looptoken, log):
+        self._dump(operations)
         self.setup()
         longevity = compute_vars_longevity(inputargs, operations)
         regalloc = ARMRegisterManager(longevity, assembler=self, frame_manager=ARMFrameManager())
@@ -376,6 +385,7 @@
 
     def assemble_bridge(self, faildescr, inputargs, operations,
                                                     original_loop_token, log):
+        self._dump(operations, 'bridge')
         self.setup()
         assert isinstance(faildescr, AbstractFailDescr)
         code = faildescr._failure_recovery_code

diff --git a/pypy/jit/backend/arm/codebuilder.py b/pypy/jit/backend/arm/codebuilder.py
--- a/pypy/jit/backend/arm/codebuilder.py
+++ b/pypy/jit/backend/arm/codebuilder.py
@@ -129,11 +129,12 @@
         raise NotImplementedError
 
     size_of_gen_load_int = 3 * WORD
-    def gen_load_int(self, r, value, c=cond.AL):
+    def gen_load_int(self, r, value, cond=cond.AL):
         """r is the register number, value is the value to be loaded to the
         register"""
-        if c != cond.AL or 0 <= value <= 0xFFFF:
-            self._load_by_shifting(r, value, c)
+        from pypy.jit.backend.arm.conditions import AL
+        if cond != AL or 0 <= value <= 0xFFFF:
+            self._load_by_shifting(r, value, cond)
         else:
             self.LDR_ri(r, reg.pc.value)
             self.MOV_rr(reg.pc.value, reg.pc.value)


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