[pypy-svn] pypy arm-backend-2: Fix some issues with call_assembler

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r42239:5b2748fcc600
Date: 2011-02-23 18:49 +0100
http://bitbucket.org/pypy/pypy/changeset/5b2748fcc600/

Log:	Fix some issues with call_assembler

diff --git a/pypy/jit/backend/arm/assembler.py b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -376,7 +376,8 @@
         self.gen_func_prolog()
         sp_patch_location = self._prepare_sp_patch_position()
         arglocs = self.gen_bootstrap_code(inputargs, regalloc, looptoken)
-
+        #for x in range(5):
+        #    self.mc.NOP()
         loop_head = self.mc.currpos()
 
         looptoken._arm_loop_code = loop_head
@@ -384,7 +385,7 @@
 
         self._walk_operations(operations, regalloc)
 
-        looptoken._arm_frame_depth = regalloc.frame_manager.frame_depth 
+        looptoken._arm_frame_depth = regalloc.frame_manager.frame_depth
         self._patch_sp_offset(sp_patch_location, looptoken)
 
         self.align()
@@ -420,7 +421,7 @@
 
         self._walk_operations(operations, regalloc)
 
-        original_loop_token._arm_frame_depth = regalloc.frame_manager.frame_depth 
+        original_loop_token._arm_frame_depth = regalloc.frame_manager.frame_depth
         self._patch_sp_offset(sp_patch_location, original_loop_token)
 
         bridge_start = self.materialize_loop(original_loop_token)
@@ -575,7 +576,7 @@
                 self.mc.gen_load_int(new_loc.value, prev_loc.getint(), cond=cond)
             prev_loc = new_loc
             if not loc.is_stack():
-                return 
+                return
         if loc.is_stack() and prev_loc.is_reg():
             self.mc.STR_ri(prev_loc.value, r.fp.value, loc.position*-WORD, cond=cond)
         elif loc.is_reg() and prev_loc.is_stack():

diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -666,7 +666,7 @@
             else:
                 raise AssertionError(kind)
         # check value
-        resloc = regalloc.force_allocate_reg(resbox)
+        resloc = regalloc.try_allocate_reg(resbox)
         assert resloc is r.r0
         self.mc.gen_load_int(r.ip.value, value)
         self.mc.CMP_rr(resloc.value, r.ip.value)
@@ -709,14 +709,13 @@
             assert isinstance(fielddescr, BaseFieldDescr)
             ofs = fielddescr.offset
             resloc = regalloc.force_allocate_reg(resbox)
-            self.mov_loc_loc(arglocs[1], r.ip, cond=c.MI)
-            self.mc.MOV_ri(resloc.value, 0, cond=c.MI)
-            self.mc.STR_ri(resloc.value, r.ip.value, ofs*WORD, cond=c.MI)
+            self.mov_loc_loc(arglocs[1], r.ip)
+            self.mc.MOV_ri(resloc.value, 0)
+            self.mc.STR_ri(resloc.value, r.ip.value, ofs)
             regalloc.possibly_free_var(resbox)
 
         if op.result is not None:
             # load the return value from fail_boxes_xxx[0]
-            resloc = regalloc.force_allocate_reg(op.result)
             kind = op.result.type
             if kind == INT:
                 adr = self.fail_boxes_int.get_addr_for_num(0)
@@ -724,20 +723,21 @@
                 adr = self.fail_boxes_ptr.get_addr_for_num(0)
             else:
                 raise AssertionError(kind)
+            resloc = regalloc.force_allocate_reg(op.result)
+            regalloc.possibly_free_var(resbox)
             self.mc.gen_load_int(r.ip.value, adr)
             self.mc.LDR_ri(resloc.value, r.ip.value)
 
+        # merge point
         offset = self.mc.currpos() - jmp_pos
-        pmc = OverwritingBuilder(self.mc, jmp_pos, WORD)
-        pmc.ADD_ri(r.pc.value, r.pc.value, offset - PC_OFFSET)
+        if offset - PC_OFFSET >= 0:
+            pmc = OverwritingBuilder(self.mc, jmp_pos, WORD)
+            pmc.ADD_ri(r.pc.value, r.pc.value, offset - PC_OFFSET)
 
         self.mc.LDR_ri(r.ip.value, r.fp.value)
         self.mc.CMP_ri(r.ip.value, 0)
 
         self._emit_guard(guard_op, regalloc._prepare_guard(guard_op), c.GE)
-        regalloc.possibly_free_vars_for_op(op)
-        if op.result:
-            regalloc.possibly_free_var(op.result)
         return fcond
 
 

diff --git a/pypy/jit/backend/arm/codebuilder.py b/pypy/jit/backend/arm/codebuilder.py
--- a/pypy/jit/backend/arm/codebuilder.py
+++ b/pypy/jit/backend/arm/codebuilder.py
@@ -44,15 +44,15 @@
         self.write32(instr)
 
     def VPUSH(self, regs, cond=cond.AL):
-        nregs = len(regs) 
+        nregs = len(regs)
         assert nregs > 0 and nregs <= 16
         freg = regs[0]
         D = (freg & 0x10) >> 4
         Dd = (freg & 0xF)
-        nregs *= 2 
-        instr = (cond << 28 
-                | 0xD2D << 16 
-                | D << 22 
+        nregs *= 2
+        instr = (cond << 28
+                | 0xD2D << 16
+                | D << 22
                 | Dd << 12
                 | 0xB << 8
                 | nregs)