[pypy-svn] pypy arm-backend-2: Remove more XXX, assert some properties of the generated machine code, required by the specification

bivab commits-noreply at bitbucket.org
Fri Jan 14 10:25:01 CET 2011


Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r40662:177347fb699b
Date: 2011-01-12 15:50 +0100
http://bitbucket.org/pypy/pypy/changeset/177347fb699b/

Log:	Remove more XXX, assert some properties of the generated machine
	code, required by the specification

diff --git a/pypy/jit/backend/arm/instructions.py b/pypy/jit/backend/arm/instructions.py
--- a/pypy/jit/backend/arm/instructions.py
+++ b/pypy/jit/backend/arm/instructions.py
@@ -1,14 +1,12 @@
-# XXX ensure b value is as expected
-# XXX add not assertions for op1
 load_store = {
-    'STR_ri': {'A':0, 'op1': 0x0, 'B': 0, 'imm': True},
-    'STR_rr': {'A':1, 'op1': 0x0, 'B': 0, 'imm': False},
-    'LDR_ri': {'A':0, 'op1': 0x1, 'B': 0, 'imm': True},
-    'LDR_rr': {'A':1, 'op1': 0x1, 'B': 0, 'imm': False},
-    'STRB_ri': {'A':0, 'op1': 0x4, 'B': 0, 'imm': True},
-    'STRB_rr': {'A':1, 'op1': 0x4, 'B': 0, 'imm': False},
-    'LDRB_ri': {'A':0, 'op1': 0x5, 'B': 0, 'imm': True},
-    'LDRB_rr': {'A':1, 'op1': 0x5, 'B': 0, 'imm': False},
+    'STR_ri': {'A':0, 'op1': 0x0, 'op1not': 0x2, 'imm': True},
+    'STR_rr': {'A':1, 'op1': 0x0, 'op1not': 0x2, 'B': 0, 'imm': False},
+    'LDR_ri': {'A':0, 'op1': 0x1, 'op1not': 0x3, 'imm': True},
+    'LDR_rr': {'A':1, 'op1': 0x1, 'op1not': 0x3, 'B': 0, 'imm': False},
+    'STRB_ri': {'A':0, 'op1': 0x4, 'op1not': 0x6, 'rn':'!0xF', 'imm': True},
+    'STRB_rr': {'A':1, 'op1': 0x4, 'op1not': 0x6, 'B': 0, 'imm': False},
+    'LDRB_ri': {'A':0, 'op1': 0x5, 'op1not': 0x7, 'rn':'!0xF', 'imm': True},
+    'LDRB_rr': {'A':1, 'op1': 0x5, 'op1not': 0x7, 'B': 0, 'imm': False},
 }
 extra_load_store = { #Section 5.2.8
     'STRH_rr':  {'op2': 0x1, 'op1': 0x0},
@@ -74,23 +72,23 @@
 }
 
 data_proc_imm = {
-    'AND_ri': {'op': 0, 'rncond':'', 'result':True, 'base':True},
-    'EOR_ri': {'op': 0x2, 'rncond':'', 'result':True, 'base':True},
-    'SUB_ri': {'op': 0x4, 'rncond':'!0xF', 'result':True, 'base':True},
+    'AND_ri': {'op': 0, 'result':True, 'base':True},
+    'EOR_ri': {'op': 0x2, 'result':True, 'base':True},
+    'SUB_ri': {'op': 0x4, 'rn':'!0xF', 'result':True, 'base':True},
     #'ADR_ri': {'op': 0x4, 'rncond':'0xF', 'result':True, 'base':True},
-    'RSB_ri': {'op': 0x6, 'rncond':'', 'result':True, 'base':True},
-    'ADD_ri': {'op': 0x8, 'rncond':'!0xF', 'result':True, 'base':True},
-    'ADC_ri': {'op': 0xA, 'rncond':'', 'result':True, 'base':True},
-    'SBC_ri': {'op': 0xC, 'rncond':'', 'result':True, 'base':True},
-    'RSC_ri': {'op': 0xE, 'rncond':'', 'result':True, 'base':True},
-    'TST_ri': {'op': 0x11, 'rncond':'', 'result':False, 'base':True},
-    'TEQ_ri': {'op': 0x13, 'rncond':'', 'result':False, 'base':True},
-    'CMP_ri': {'op': 0x15, 'rncond':'', 'result':False, 'base':True},
-    'CMN_ri': {'op': 0x17, 'rncond':'', 'result':False, 'base':True},
-    'ORR_ri': {'op': 0x18, 'rncond':'', 'result':True, 'base':True},
-    'MOV_ri': {'op': 0x1A, 'rncond':'', 'result':True, 'base':False},
-    'BIC_ri': {'op': 0x1C, 'rncond':'', 'result':True, 'base':True},
-    'MVN_ri': {'op': 0x1E, 'rncond':'', 'result':True, 'base':False},
+    'RSB_ri': {'op': 0x6, 'result':True, 'base':True},
+    'ADD_ri': {'op': 0x8, 'rn':'!0xF', 'result':True, 'base':True},
+    'ADC_ri': {'op': 0xA, 'result':True, 'base':True},
+    'SBC_ri': {'op': 0xC, 'result':True, 'base':True},
+    'RSC_ri': {'op': 0xE, 'result':True, 'base':True},
+    'TST_ri': {'op': 0x11, 'result':False, 'base':True},
+    'TEQ_ri': {'op': 0x13, 'result':False, 'base':True},
+    'CMP_ri': {'op': 0x15, 'result':False, 'base':True},
+    'CMN_ri': {'op': 0x17, 'result':False, 'base':True},
+    'ORR_ri': {'op': 0x18, 'result':True, 'base':True},
+    'MOV_ri': {'op': 0x1A, 'result':True, 'base':False},
+    'BIC_ri': {'op': 0x1C, 'result':True, 'base':True},
+    'MVN_ri': {'op': 0x1E, 'result':True, 'base':False},
 }
 
 supervisor_and_coproc = {

diff --git a/pypy/jit/backend/arm/instruction_builder.py b/pypy/jit/backend/arm/instruction_builder.py
--- a/pypy/jit/backend/arm/instruction_builder.py
+++ b/pypy/jit/backend/arm/instruction_builder.py
@@ -5,30 +5,44 @@
     #  XXX W and P bits are not encoded yet
     n = (0x1 << 26
         | (table['A'] & 0x1) << 25
-        | (table['op1'] & 0x1F) << 20
-        | (table['B'] & 0x1) << 4)
+        | (table['op1'] & 0x1F) << 20)
+    if 'B' in table:
+        b_zero = True
+    else:
+        b_zero = False
+    op1cond = table['op1not']
+    rncond = ('rn' in table and table['rn'] == '!0xF')
     if table['imm']:
+        assert not b_zero
         def f(self, rt, rn, imm=0, cond=cond.AL):
+            assert not (rncond and rn == 0xF)
             p = 1
             w = 0
             u, imm = self._encode_imm(imm)
-            self.write32(n
+            instr = (n
                     | cond << 28
                     | (p & 0x1) <<  24
                     | (u & 0x1) << 23
                     | (w & 0x1) << 21
                     | imm_operation(rt, rn, imm))
+            assert instr & 0x1F00000 != op1cond
+            self.write32(instr)
     else:
         def f(self, rt, rn, rm, imm=0, cond=cond.AL, s=0, shifttype=0):
+            assert not (rncond and rn == 0xF)
             p = 1
             w = 0
             u, imm = self._encode_imm(imm)
-            self.write32(n
-                        | cond << 28
-                        | (p & 0x1) <<  24
-                        | (u & 0x1) << 23
-                        | (w & 0x1) << 21
-                        | reg_operation(rt, rn, rm, imm, s, shifttype))
+            instr = (n
+                    | cond << 28
+                    | (p & 0x1) <<  24
+                    | (u & 0x1) << 23
+                    | (w & 0x1) << 21
+                    | reg_operation(rt, rn, rm, imm, s, shifttype))
+            if b_zero:
+                assert instr & 0x10 == 0, 'bit 4 should be zero'
+            assert instr & 0x1F00000 != op1cond
+            self.write32(instr)
     return f
 
 def define_extra_load_store_func(name, table):
@@ -104,25 +118,26 @@
 def define_data_proc_imm_func(name, table):
     n = (0x1 << 25
         | (table['op'] & 0x1F) << 20)
+    rncond = ('rn' in table and table['rn'] == '!0xF')
     if table['result'] and table['base']:
         def imm_func(self, rd, rn, imm=0, cond=cond.AL, s=0):
             if imm < 0:
                 raise ValueError
-            # XXX check condition on rn
+            assert not (rncond and rn == 0xF)
             self.write32(n
                 | cond << 28
                 | s << 20
                 | imm_operation(rd, rn, imm))
     elif not table['base']:
         def imm_func(self, rd, imm=0, cond=cond.AL, s=0):
-            # XXX check condition on rn
+            assert not (rncond and rn == 0xF)
             self.write32(n
                 | cond << 28
                 | s << 20
                 | imm_operation(rd, 0, imm))
     else:
         def imm_func(self, rn, imm=0, cond=cond.AL, s=0):
-            # XXX check condition on rn
+            assert not (rncond and rn == 0xF)
             self.write32(n
                 | cond << 28
                 | s << 20


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