[pypy-svn] pypy arm-backend-2: Start implementing encoding for 64-bit floating point operations

bivab commits-noreply at bitbucket.org
Mon Jan 17 10:54:38 CET 2011


Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r40748:a9071318a782
Date: 2011-01-16 18:20 +0100
http://bitbucket.org/pypy/pypy/changeset/a9071318a782/

Log:	Start implementing encoding for 64-bit floating point operations

diff --git a/pypy/jit/backend/arm/instructions.py b/pypy/jit/backend/arm/instructions.py
--- a/pypy/jit/backend/arm/instructions.py
+++ b/pypy/jit/backend/arm/instructions.py
@@ -119,3 +119,10 @@
     'SMULL': {'op':0xC, 'long': True},
     'SMLAL': {'op':0xE, 'long': True},
 }
+
+# based on encoding from A7.5	VFP data-processing instructions
+# opc2 is one of the parameters and therefore ignored here
+float64_data_proc_instructions = {
+    'VADD': {'opc1':0x3, 'opc3':0},
+    'VSUB': {'opc1':0x3, 'opc3':1},
+}

diff --git a/pypy/jit/backend/arm/test/test_instr_codebuilder.py b/pypy/jit/backend/arm/test/test_instr_codebuilder.py
--- a/pypy/jit/backend/arm/test/test_instr_codebuilder.py
+++ b/pypy/jit/backend/arm/test/test_instr_codebuilder.py
@@ -129,6 +129,14 @@
         self.cb.POP([reg.value for reg in r.caller_resp], cond=conditions.AL)
         self.assert_equal('LDM SP!, {r0, r1, r2, r3}')
 
+    def test_double_add(self):
+        self.cb.VADD(r.d1.value, r.d2.value, r.d3.value, conditions.LE)
+        self.assert_equal("VADDLE.F64 D1, D2, D3")
+
+    def test_double_sub(self):
+        self.cb.VSUB(r.d1.value, r.d2.value, r.d3.value, conditions.GT)
+        self.assert_equal("VSUBGT.F64 D1, D2, D3")
+
     def test_pop_raises_on_lr(self):
         assert py.test.raises(AssertionError, 'self.cb.POP([r.lr.value])')
 
@@ -137,6 +145,13 @@
     def setup_method(self, ffuu_method):
         self.cb = CodeBuilder()
 
+def gen_test_float64_data_proc_instructions_func(name, table):
+    tests = []
+    for c,v in [('EQ', conditions.EQ), ('LE', conditions.LE), ('AL', conditions.AL)]:
+        for reg in range(16):
+            asm = 'd%d, d1, d2' % reg
+            tests.append((asm, (reg, r.d1.value, r.d2.value), {}, '.F64'))
+    return tests
 
 def gen_test_data_proc_imm_func(name, table):
     if table['result'] and table['base']:
@@ -225,6 +240,7 @@
             asm = 'r3, {%s}' % ','.join(['r%d' % i for i in range(regs+1)])
             tests.append((asm, (r.r3.value, range(regs+1))))
     return tests
+
 def build_tests():
     cls = TestInstrCodeBuilderForGeneratedInstr
     test_name = 'test_generated_%s'

diff --git a/pypy/jit/backend/arm/instruction_builder.py b/pypy/jit/backend/arm/instruction_builder.py
--- a/pypy/jit/backend/arm/instruction_builder.py
+++ b/pypy/jit/backend/arm/instruction_builder.py
@@ -279,6 +279,21 @@
 
     return f
 
+def define_float64_data_proc_instructions_func(name, table):
+    n = (0xE << 24
+        | 0x5 << 9
+        | 0x1 << 8 # 64 bit flag
+        | (table['opc1'] & 0xF) << 20
+        | (table['opc3'] & 0x3) << 6)
+    def f(self, dd, dn, dm, cond=cond.AL):
+        instr = (n
+                | (cond & 0xF) << 28
+                | (dn & 0xF) << 16
+                | (dd & 0xF) << 12
+                | (dm & 0xF))
+        self.write32(instr)
+    return f
+
 def imm_operation(rt, rn, imm):
     return ((rn & 0xFF) << 16
     | (rt & 0xFF) << 12
@@ -293,8 +308,8 @@
             | (rm & 0xF))
 
 def define_instruction(builder, key, val, target):
-        f = builder(key, val)
-        setattr(target, key, f)
+    f = builder(key, val)
+    setattr(target, key, f)
 
 def define_instructions(target):
     inss = [k for k in instructions.__dict__.keys() if not k.startswith('__')]

diff --git a/pypy/jit/backend/arm/registers.py b/pypy/jit/backend/arm/registers.py
--- a/pypy/jit/backend/arm/registers.py
+++ b/pypy/jit/backend/arm/registers.py
@@ -3,6 +3,9 @@
 registers = [RegisterLocation(i) for i in range(16)]
 r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 = registers
 
+#vfp registers interpreted as 64-bit registers
+d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15 = registers
+
 # aliases for registers
 fp = r11
 ip = r12

diff --git a/pypy/jit/backend/arm/test/gen.py b/pypy/jit/backend/arm/test/gen.py
--- a/pypy/jit/backend/arm/test/gen.py
+++ b/pypy/jit/backend/arm/test/gen.py
@@ -3,7 +3,7 @@
 from pypy.jit.backend.arm.test.support import AS
 class ASMInstruction(object):
 
-    asm_opts = '-mcpu=cortex-a8 -march=armv7'
+    asm_opts = '-mfpu=neon -mcpu=cortex-a8 -march=armv7-a'
     body = """.section .text
 .arm
 _start: .global _start


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