[pypy-svn] pypy arm-backend-2: Implement VPUSH instruction

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r40773:258e6425805c
Date: 2011-01-17 13:09 +0100
http://bitbucket.org/pypy/pypy/changeset/258e6425805c/

Log:	Implement VPUSH instruction

diff --git a/pypy/jit/backend/arm/test/test_instr_codebuilder.py b/pypy/jit/backend/arm/test/test_instr_codebuilder.py
--- a/pypy/jit/backend/arm/test/test_instr_codebuilder.py
+++ b/pypy/jit/backend/arm/test/test_instr_codebuilder.py
@@ -91,6 +91,18 @@
         self.cb.PUSH([reg.value for reg in [r.fp, r.ip, r.lr, r.pc]])
         self.assert_equal('PUSH {fp, ip, lr, pc}')
 
+    def test_vpush_one_reg(self):
+        self.cb.VPUSH([r.d3.value])
+        self.assert_equal('VPUSH {d3}')
+
+    def test_vpush_one_reg2(self):
+        self.cb.VPUSH([r.d12.value])
+        self.assert_equal('VPUSH {d12}')
+
+    def test_vpush_multiple(self):
+        self.cb.VPUSH([reg.value for reg in [r.d11, r.d12, r.d13, r.d14, r.d15]])
+        self.assert_equal('VPUSH {D11, D12, D13, D14, D15}')
+
     def test_sub_ri(self):
         self.cb.SUB_ri(r.r2.value, r.r4.value, 123)
         self.assert_equal('SUB r2, r4, #123')

diff --git a/pypy/jit/backend/arm/codebuilder.py b/pypy/jit/backend/arm/codebuilder.py
--- a/pypy/jit/backend/arm/codebuilder.py
+++ b/pypy/jit/backend/arm/codebuilder.py
@@ -43,6 +43,21 @@
         instr = self._encode_reg_list(cond << 28 | 0x92D << 16, regs)
         self.write32(instr)
 
+    def VPUSH(self, regs, cond=cond.AL):
+        nregs = len(regs) 
+        assert nregs > 0 and nregs <= 16
+        freg = regs[0]
+        D = (freg & 0x10) >> 4
+        Dd = (freg & 0xF)
+        nregs *= 2 
+        instr = (cond << 28 
+                | 0xD2D << 16 
+                | D << 22 
+                | Dd << 12
+                | 0xB << 8
+                | nregs)
+        self.write32(instr)
+
     def POP(self, regs, cond=cond.AL):
         assert reg.lr.value not in regs
         instr = self._encode_reg_list(cond << 28 | 0x8BD << 16, regs)