[pypy-svn] pypy default: (David Edelsohn) make the x86 backend no longer emit the XCHG, which implies

[cfbolz]

Author: Carl Friedrich Bolz <cfbolz at gmx.de>
Branch: 
Changeset: r42466:6599d8ca8be1
Date: 2011-03-07 21:51 +0100
http://bitbucket.org/pypy/pypy/changeset/6599d8ca8be1/

Log:	(David Edelsohn) make the x86 backend no longer emit the XCHG, which
	implies atomic semantics (which is not really needed in our case).

diff --git a/pypy/jit/backend/x86/rx86.py b/pypy/jit/backend/x86/rx86.py
--- a/pypy/jit/backend/x86/rx86.py
+++ b/pypy/jit/backend/x86/rx86.py
@@ -516,8 +516,8 @@
 
     # XXX: Only here for testing purposes..."as" happens the encode the
     # registers in the opposite order that we would otherwise do in a
-    # register-register exchange
-    XCHG_rr = insn(rex_w, '\x87', register(1), register(2,8), '\xC0')
+    # register-register exchange.
+    #XCHG_rr = insn(rex_w, '\x87', register(1), register(2,8), '\xC0')
 
     JMP_l = insn('\xE9', relative(1))
     JMP_r = insn(rex_nw, '\xFF', orbyte(4<<3), register(1), '\xC0')
@@ -658,7 +658,7 @@
 define_modrm_modes('MOVSD_x*', ['\xF2', rex_nw, '\x0F\x10', register(1,8)], regtype='XMM')
 define_modrm_modes('MOVSD_*x', ['\xF2', rex_nw, '\x0F\x11', register(2,8)], regtype='XMM')
 
-define_modrm_modes('XCHG_r*', [rex_w, '\x87', register(1, 8)])
+#define_modrm_modes('XCHG_r*', [rex_w, '\x87', register(1, 8)])
 
 define_modrm_modes('ADDSD_x*', ['\xF2', rex_nw, '\x0F\x58', register(1, 8)], regtype='XMM')
 define_modrm_modes('SUBSD_x*', ['\xF2', rex_nw, '\x0F\x5C', register(1, 8)], regtype='XMM')

diff --git a/pypy/jit/backend/x86/assembler.py b/pypy/jit/backend/x86/assembler.py
--- a/pypy/jit/backend/x86/assembler.py
+++ b/pypy/jit/backend/x86/assembler.py
@@ -698,11 +698,9 @@
             else:
                 target = tmp
             if inputargs[i].type == REF:
-                # This uses XCHG to put zeroes in fail_boxes_ptr after
-                # reading them
-                self.mc.XOR(target, target)
                 adr = self.fail_boxes_ptr.get_addr_for_num(i)
-                self.mc.XCHG(target, heap(adr))
+                self.mc.MOV(target, heap(adr))
+                self.mc.MOV(heap(adr), imm0)
             else:
                 adr = self.fail_boxes_int.get_addr_for_num(i)
                 self.mc.MOV(target, heap(adr))
@@ -1908,8 +1906,8 @@
                     self.mc.MOV(eax, heap(adr))
                 elif kind == REF:
                     adr = self.fail_boxes_ptr.get_addr_for_num(0)
-                    self.mc.XOR_rr(eax.value, eax.value)
-                    self.mc.XCHG(eax, heap(adr))
+                    self.mc.MOV(eax, heap(adr))
+                    self.mc.MOV(heap(adr), imm0)
                 else:
                     raise AssertionError(kind)
         #

diff --git a/pypy/jit/backend/x86/test/test_rx86.py b/pypy/jit/backend/x86/test/test_rx86.py
--- a/pypy/jit/backend/x86/test/test_rx86.py
+++ b/pypy/jit/backend/x86/test/test_rx86.py
@@ -118,11 +118,6 @@
     s.SET_ir(5, dl)
     assert s.getvalue() == '\x0F\x95\xC2'
 
-def test_xchg_rj():
-    s = CodeBuilder32()
-    s.XCHG_rj(edx, 0x01234567)
-    assert s.getvalue() == '\x87\x15\x67\x45\x23\x01'
-
 def test_movsd_rj():
     s = CodeBuilder32()
     s.MOVSD_xj(xmm2, 0x01234567)

diff --git a/pypy/jit/backend/x86/regloc.py b/pypy/jit/backend/x86/regloc.py
--- a/pypy/jit/backend/x86/regloc.py
+++ b/pypy/jit/backend/x86/regloc.py
@@ -491,7 +491,9 @@
     MOVSX16 = _binaryop('MOVSX16')
     MOV32 = _binaryop('MOV32')
     MOVSX32 = _binaryop('MOVSX32')
-    XCHG = _binaryop('XCHG')
+    # Avoid XCHG because it always implies atomic semantics, which is
+    # slower and does not pair well for dispatch.
+    #XCHG = _binaryop('XCHG')
 
     PUSH = _unaryop('PUSH')
     POP = _unaryop('POP')