[pypy-commit] pypy ppc-jit-backend: Implemented INT_AND, INT_OR, INT_XOR.

[hager]

Author: hager <sven.hager at uni-duesseldorf.de>
Branch: ppc-jit-backend
Changeset: r48206:b7a4abd18923
Date: 2011-10-18 15:23 +0200
http://bitbucket.org/pypy/pypy/changeset/b7a4abd18923/

Log:	Implemented INT_AND, INT_OR, INT_XOR.

diff --git a/pypy/jit/backend/ppc/ppcgen/opassembler.py b/pypy/jit/backend/ppc/ppcgen/opassembler.py
--- a/pypy/jit/backend/ppc/ppcgen/opassembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/opassembler.py
@@ -72,6 +72,18 @@
         self.mc.subf(r.r0.value, r.r0.value, l0.value)
         self.mc.mr(res.value, r.r0.value)
 
+    def emit_int_and(self, op, arglocs, regalloc):
+        l0, l1, res = arglocs
+        self.mc.and_(res.value, l0.value, l1.value)
+
+    def emit_int_or(self, op, arglocs, regalloc):
+        l0, l1, res = arglocs
+        self.mc.or_(res.value, l0.value, l1.value)
+
+    def emit_int_xor(self, op, arglocs, regalloc):
+        l0, l1, res = arglocs
+        self.mc.xor(res.value, l0.value, l1.value)
+
     emit_int_le = gen_emit_cmp_op(c.LE)   
 
     def _emit_guard(self, op, arglocs, fcond, save_exc=False,
diff --git a/pypy/jit/backend/ppc/ppcgen/regalloc.py b/pypy/jit/backend/ppc/ppcgen/regalloc.py
--- a/pypy/jit/backend/ppc/ppcgen/regalloc.py
+++ b/pypy/jit/backend/ppc/ppcgen/regalloc.py
@@ -222,6 +222,15 @@
     def prepare_int_mod(self, op):
         return self.prepare_int_mul(op)
 
+    def prepare_int_and(self, op):
+        return self.prepare_int_mul(op)
+
+    def prepare_int_or(self, op):
+        return self.prepare_int_mul(op)
+
+    def prepare_int_xor(self, op):
+        return self.prepare_int_mul(op)
+
     def prepare_finish(self, op):
         args = [locations.imm(self.frame_manager.frame_depth)]
         for i in range(op.numargs()):