[pypy-commit] pypy arm-backend-2: use shifted immediate and reg arguments for the operations

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r52059:fe97ecdb2301
Date: 2012-01-26 16:29 +0100
http://bitbucket.org/pypy/pypy/changeset/fe97ecdb2301/

Log:	use shifted immediate and reg arguments for the operations

diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -591,15 +591,15 @@
                 tmp1 = loc_index
                 # store additional scratch reg
                 self.mc.PUSH([tmp1.value])
+                #byteofs
+                s = 3 + descr.jit_wb_card_page_shift
+                self.mc.MVN_rr(r.lr.value, tmp1.value,
+                                    imm=s, shifttype=shift.LSR)
                 # byte_index
-                self.mc.LSR_ri(tmp1.value, tmp1.value,
-                            imm=descr.jit_wb_card_page_shift)
-                #byteofs
-                self.mc.LSR_ri(r.lr.value, tmp1.value, imm=3)
-                self.mc.MVN_rr(r.lr.value, r.lr.value)
-                #byteval
+                self.mc.MOV_ri(r.ip.value, imm=7)
+                self.mc.AND_rr(tmp1.value, r.ip.value, tmp1.value,
+                            imm=descr.jit_wb_card_page_shift, shifttype=shift.LSR)
                 self.mc.MOV_ri(r.ip.value, imm=1)
-                self.mc.AND_ri(tmp1.value, tmp1.value, imm=7)
                 self.mc.LSL_rr(tmp1.value, r.ip.value, tmp1.value)
 
                 # set the bit