[pypy-commit] pypy arm-backend-2: remove the case where loc_index is an immediate as it does not happen in our case and move the allocation of the scratch registers to the register allocator

bivab noreply at buildbot.pypy.org
Fri Feb 3 12:33:42 CET 2012


Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r52062:001a7119b6ba
Date: 2012-01-26 19:36 +0100
http://bitbucket.org/pypy/pypy/changeset/001a7119b6ba/

Log:	remove the case where loc_index is an immediate as it does not
	happen in our case and move the allocation of the scratch registers
	to the register allocator

diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -584,38 +584,29 @@
             # patch the JNZ above
             offset = self.mc.currpos()
             pmc = OverwritingBuilder(self.mc, jnz_location, WORD)
-            pmc.B_offs(offset, c.NE)  #NZ?
+            pmc.B_offs(offset, c.NE)
             #
             loc_index = arglocs[1]
-            if loc_index.is_reg():
-                tmp1 = regalloc.get_scratch_reg(INT, [loc_index, loc_base])
-                tmp2 = regalloc.get_scratch_reg(INT, [tmp1, loc_base])
-                # store additional scratch reg
-                #byteofs
-                s = 3 + descr.jit_wb_card_page_shift
-                self.mc.MVN_rr(r.lr.value, loc_index.value,
-                                    imm=s, shifttype=shift.LSR)
-                # byte_index
-                self.mc.MOV_ri(r.ip.value, imm=7)
-                self.mc.AND_rr(tmp1.value, r.ip.value, loc_index.value,
-                        imm=descr.jit_wb_card_page_shift, shifttype=shift.LSR)
+            assert loc_index.is_reg()
+            tmp1 = arglocs[-2]
+            tmp2 = arglocs[-1]
+            #byteofs
+            s = 3 + descr.jit_wb_card_page_shift
+            self.mc.MVN_rr(r.lr.value, loc_index.value,
+                                imm=s, shifttype=shift.LSR)
+            # byte_index
+            self.mc.MOV_ri(r.ip.value, imm=7)
+            self.mc.AND_rr(tmp1.value, r.ip.value, loc_index.value,
+                    imm=descr.jit_wb_card_page_shift, shifttype=shift.LSR)
 
-                # set the bit
-                self.mc.MOV_ri(tmp2.value, imm=1)
-                self.mc.LDRB_rr(r.ip.value, loc_base.value, r.lr.value)
-                self.mc.ORR_rr_sr(r.ip.value, r.ip.value, tmp2.value,
-                                        tmp1.value, shifttype=shift.LSL)
-                self.mc.STRB_rr(r.ip.value, loc_base.value, r.lr.value)
-                # done
-            elif loc_index.is_imm():
-                byte_index = loc_index.value >> descr.jit_wb_card_page_shift
-                byte_ofs = ~(byte_index >> 3)
-                byte_val = 1 << (byte_index & 7)
-                self.mc.LDRB_ri(r.ip.value, loc_base.value, byte_ofs)
-                self.mc.ORR_ri(r.ip.value, r.ip.value, imm=byte_val)
-                self.mc.STRB_ri(r.ip.value, loc_base.value, byte_ofs)
-            else:
-                raise AssertionError("index is neither RegLoc nor ImmedLoc")
+            # set the bit
+            self.mc.MOV_ri(tmp2.value, imm=1)
+            self.mc.LDRB_rr(r.ip.value, loc_base.value, r.lr.value)
+            self.mc.ORR_rr_sr(r.ip.value, r.ip.value, tmp2.value,
+                                    tmp1.value, shifttype=shift.LSL)
+            self.mc.STRB_rr(r.ip.value, loc_base.value, r.lr.value)
+            # done
+
             # patch the JMP above
             offset = self.mc.currpos()
             pmc = OverwritingBuilder(self.mc, jmp_location, WORD)
diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -988,14 +988,22 @@
     def prepare_op_cond_call_gc_wb(self, op, fcond):
         assert op.result is None
         N = op.numargs()
-        # we force all arguments in a reg (unless they are Consts),
-        # because it will be needed anyway by the following setfield_gc
-        # or setarrayitem_gc. It avoids loading it twice from the memory.
+        # we force all arguments in a reg because it will be needed anyway by
+        # the following setfield_gc or setarrayitem_gc. It avoids loading it
+        # twice from the memory.
         arglocs = []
         args = op.getarglist()
         for i in range(N):
             loc = self._ensure_value_is_boxed(op.getarg(i), args)
             arglocs.append(loc)
+        card_marking = False
+        if op.getopnum() == rop.COND_CALL_GC_WB_ARRAY:
+            card_marking = op.getdescr().jit_wb_cards_set != 0
+        if card_marking:  # allocate scratch registers
+            tmp1 = self.get_scratch_reg(INT)
+            tmp2 = self.get_scratch_reg(INT)
+            arglocs.append(tmp1)
+            arglocs.append(tmp2)
         return arglocs
 
     prepare_op_cond_call_gc_wb_array = prepare_op_cond_call_gc_wb


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