[pypy-commit] pypy arm-backend-2: (arigo, bivab) implement the BLX ARM instruction to branch to an address stored in a register

bivab noreply at buildbot.pypy.org
Fri Jan 20 17:17:20 CET 2012


Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r51547:95557903da83
Date: 2012-01-20 17:11 +0100
http://bitbucket.org/pypy/pypy/changeset/95557903da83/

Log:	(arigo, bivab) implement the BLX ARM instruction to branch to an
	address stored in a register

diff --git a/pypy/jit/backend/arm/codebuilder.py b/pypy/jit/backend/arm/codebuilder.py
--- a/pypy/jit/backend/arm/codebuilder.py
+++ b/pypy/jit/backend/arm/codebuilder.py
@@ -178,14 +178,11 @@
 
     def BL(self, addr, c=cond.AL):
         target = rffi.cast(rffi.INT, addr)
-        if c == cond.AL:
-            self.ADD_ri(reg.lr.value, reg.pc.value, arch.PC_OFFSET / 2)
-            self.LDR_ri(reg.pc.value, reg.pc.value, imm=-arch.PC_OFFSET / 2)
-            self.write32(target)
-        else:
-            self.gen_load_int(reg.ip.value, target, cond=c)
-            self.MOV_rr(reg.lr.value, reg.pc.value, cond=c)
-            self.MOV_rr(reg.pc.value, reg.ip.value, cond=c)
+        self.gen_load_int(reg.ip.value, target, cond=c)
+        self.BLX(reg.ip.value)
+
+    def BLX(self, reg, c=cond.AL):
+        self.write32(c << 28 | 0x12FFF3 << 4 | (reg & 0xF))
 
     def MOVT_ri(self, rd, imm16, c=cond.AL):
         """Move Top writes an immediate value to the top halfword of the


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