[pypy-commit] pypy py3k: merge default
pjenvey
noreply at buildbot.pypy.org
Wed Nov 20 02:45:49 CET 2013
Author: Philip Jenvey <pjenvey at underboss.org>
Branch: py3k
Changeset: r68255:6331cf185f84
Date: 2013-11-19 17:44 -0800
http://bitbucket.org/pypy/pypy/changeset/6331cf185f84/
Log: merge default
diff --git a/lib-python/2.7/test/test_multiprocessing.py b/lib-python/2.7/test/test_multiprocessing.py
--- a/lib-python/2.7/test/test_multiprocessing.py
+++ b/lib-python/2.7/test/test_multiprocessing.py
@@ -1,5 +1,10 @@
#!/usr/bin/env python
+## FIXME: remove when https://bugs.pypy.org/issue1644 is resolved
+import sys
+if sys.platform.startswith('freebsd'):
+ raise Exception("This test hangs on FreeBSD. Test deactivated for now until https://bugs.pypy.org/issue1644 get resolved")
+
#
# Unit tests for the multiprocessing package
#
diff --git a/pypy/doc/whatsnew-head.rst b/pypy/doc/whatsnew-head.rst
--- a/pypy/doc/whatsnew-head.rst
+++ b/pypy/doc/whatsnew-head.rst
@@ -10,6 +10,8 @@
.. branch: numpy-newbyteorder
Clean up numpy types, add newbyteorder functionality
-.. branch windows-packaging
+.. branch: windows-packaging
Package tk/tcl runtime with win32
+.. branch: armhf-singlefloat
+JIT support for singlefloats on ARM using the hardfloat ABI
diff --git a/pypy/module/micronumpy/interp_dtype.py b/pypy/module/micronumpy/interp_dtype.py
--- a/pypy/module/micronumpy/interp_dtype.py
+++ b/pypy/module/micronumpy/interp_dtype.py
@@ -151,6 +151,14 @@
endian = NPY_NATBYTE
return space.wrap("%s%s%s" % (endian, basic, size))
+ def descr_get_descr(self, space):
+ if not self.is_record_type():
+ return space.newlist([space.newtuple([space.wrap(""),
+ self.descr_get_str(space)])])
+ else:
+ raise OperationError(space.w_NotImplementedError, space.wrap(
+ "descr not implemented for record types"))
+
def descr_get_base(self, space):
return space.wrap(self.base)
@@ -448,6 +456,7 @@
fields = GetSetProperty(W_Dtype.descr_get_fields),
names = GetSetProperty(W_Dtype.descr_get_names),
hasobject = GetSetProperty(W_Dtype.descr_get_hasobject),
+ descr = GetSetProperty(W_Dtype.descr_get_descr),
)
W_Dtype.typedef.acceptable_as_base_class = False
diff --git a/pypy/module/micronumpy/interp_numarray.py b/pypy/module/micronumpy/interp_numarray.py
--- a/pypy/module/micronumpy/interp_numarray.py
+++ b/pypy/module/micronumpy/interp_numarray.py
@@ -93,7 +93,11 @@
def descr_fill(self, space, w_value):
self.fill(self.get_dtype().coerce(space, w_value))
- def descr_tostring(self, space):
+ def descr_tostring(self, space, w_order=None):
+ order = order_converter(space, w_order, NPY_CORDER)
+ if order == NPY_FORTRANORDER:
+ raise OperationError(space.w_NotImplementedError, space.wrap(
+ "unsupported value for order"))
return space.wrap(loop.tostring(space, self))
def getitem_filter(self, space, arr):
diff --git a/pypy/module/micronumpy/test/test_dtypes.py b/pypy/module/micronumpy/test/test_dtypes.py
--- a/pypy/module/micronumpy/test/test_dtypes.py
+++ b/pypy/module/micronumpy/test/test_dtypes.py
@@ -831,6 +831,17 @@
assert x.dtype == int8
assert (x == array(42)).all()
+ def test_descr(self):
+ import numpy as np
+ assert np.dtype('<i8').descr == [('', '<i8')]
+ assert np.dtype('|S4').descr == [('', '|S4')]
+ d = [('test', '<i8'), ('blah', '<i2', (2, 3))]
+ import sys
+ if '__pypy__' in sys.builtin_module_names:
+ raises(NotImplementedError, "np.dtype(d).descr")
+ else:
+ assert np.dtype(d).descr == d
+
class AppTestStrUnicodeDtypes(BaseNumpyAppTest):
def test_mro(self):
from numpypy import str_, unicode_, character, flexible, generic
diff --git a/pypy/module/micronumpy/test/test_numarray.py b/pypy/module/micronumpy/test/test_numarray.py
--- a/pypy/module/micronumpy/test/test_numarray.py
+++ b/pypy/module/micronumpy/test/test_numarray.py
@@ -68,7 +68,8 @@
assert s.start == 1
assert s.strides == [2, 10, 50]
assert s.backstrides == [6, 40, 100]
- s = create_slice(self.space, a, [Chunk(1, 5, 3, 2), Chunk(1, 2, 1, 1), Chunk(1, 0, 0, 1)])
+ s = create_slice(self.space, a, [Chunk(1, 5, 3, 2), Chunk(1, 2, 1, 1),
+ Chunk(1, 0, 0, 1)])
assert s.shape == [2, 1]
assert s.strides == [3, 10]
assert s.backstrides == [3, 0]
@@ -2043,7 +2044,8 @@
a = array([1, 2], dtype="int64")
data = a.__reduce__()
- assert data[2][4] == '\x01\x00\x00\x00\x00\x00\x00\x00\x02\x00\x00\x00\x00\x00\x00\x00'
+ assert data[2][4] == '\x01\x00\x00\x00\x00\x00\x00\x00' \
+ '\x02\x00\x00\x00\x00\x00\x00\x00'
pickled_data = dumps(a)
assert (loads(pickled_data) == a).all()
@@ -2791,9 +2793,11 @@
assert k[0] == dtype('float16').type(5.)
dt = array([5],dtype='longfloat').dtype
if dt.itemsize == 12:
- m = fromstring('\x00\x00\x00\x00\x00\x00\x00\xa0\x01@\x00\x00', dtype='float96')
+ m = fromstring('\x00\x00\x00\x00\x00\x00\x00\xa0\x01@\x00\x00',
+ dtype='float96')
elif dt.itemsize == 16:
- m = fromstring('\x00\x00\x00\x00\x00\x00\x00\xa0\x01@\x00\x00\x00\x00\x00\x00', dtype='float128')
+ m = fromstring('\x00\x00\x00\x00\x00\x00\x00\xa0\x01@\x00\x00' \
+ '\x00\x00\x00\x00', dtype='float128')
elif dt.itemsize == 8:
skip('longfloat is float64')
else:
@@ -2816,6 +2820,15 @@
assert array([1, 2, 3], '<i2')[::2].tostring() == '\x01\x00\x03\x00'
assert array([1, 2, 3], '>i2')[::2].tostring() == '\x00\x01\x00\x03'
assert array(0, dtype='i2').tostring() == '\x00\x00'
+ a = array([[1, 2], [3, 4]], dtype='i1')
+ for order in (None, False, 'C', 'K', 'a'):
+ assert a.tostring(order) == '\x01\x02\x03\x04'
+ import sys
+ for order in (True, 'F'):
+ if '__pypy__' in sys.builtin_module_names:
+ raises(NotImplementedError, a.tostring, order)
+ else:
+ assert a.tostring(order) == '\x01\x03\x02\x04'
class AppTestRepr(BaseNumpyAppTest):
@@ -3019,7 +3032,8 @@
from numpypy import dtype, array, zeros
d = dtype([("x", "int", 3), ("y", "float", 5)])
- a = array([([1, 2, 3], [0.5, 1.5, 2.5, 3.5, 4.5]), ([4, 5, 6], [5.5, 6.5, 7.5, 8.5, 9.5])], dtype=d)
+ a = array([([1, 2, 3], [0.5, 1.5, 2.5, 3.5, 4.5]),
+ ([4, 5, 6], [5.5, 6.5, 7.5, 8.5, 9.5])], dtype=d)
for v in ['x', u'x', 0, -2]:
assert (a[0][v] == [1, 2, 3]).all()
@@ -3029,7 +3043,8 @@
assert (a[1][v] == [5.5, 6.5, 7.5, 8.5, 9.5]).all()
for v in [-3, 2]:
exc = raises(IndexError, "a[0][%d]" % v)
- assert exc.value.message == "invalid index (%d)" % (v + 2 if v < 0 else v)
+ assert exc.value.message == "invalid index (%d)" % \
+ (v + 2 if v < 0 else v)
exc = raises(IndexError, "a[0]['z']")
assert exc.value.message == "invalid index"
exc = raises(IndexError, "a[0][None]")
@@ -3099,7 +3114,8 @@
from numpypy import dtype, array
d = dtype([("x", "int", 3), ("y", "float", 5)])
- a = array([([1, 2, 3], [0.5, 1.5, 2.5, 3.5, 4.5]), ([4, 5, 6], [5.5, 6.5, 7.5, 8.5, 9.5])], dtype=d)
+ a = array([([1, 2, 3], [0.5, 1.5, 2.5, 3.5, 4.5]),
+ ([4, 5, 6], [5.5, 6.5, 7.5, 8.5, 9.5])], dtype=d)
assert len(list(a[0])) == 2
diff --git a/rpython/jit/backend/arm/callbuilder.py b/rpython/jit/backend/arm/callbuilder.py
--- a/rpython/jit/backend/arm/callbuilder.py
+++ b/rpython/jit/backend/arm/callbuilder.py
@@ -227,20 +227,81 @@
class HardFloatCallBuilder(ARMCallbuilder):
+ next_arg_vfp = 0
+ next_arg_svfp = 0
+
+ def get_next_vfp(self, tp):
+ assert tp in 'fS'
+ if self.next_arg_vfp == -1:
+ return None
+ if tp == 'S':
+ i = self.next_arg_svfp
+ next_vfp = (i >> 1) + 1
+ if not (i + 1) & 1: # i is even
+ self.next_arg_vfp = max(self.next_arg_vfp, next_vfp)
+ self.next_arg_svfp = self.next_arg_vfp << 1
+ else:
+ self.next_arg_svfp += 1
+ self.next_arg_vfp = next_vfp
+ lst = r.svfp_argument_regs
+ else: # 64bit double
+ i = self.next_arg_vfp
+ self.next_arg_vfp += 1
+ if self.next_arg_svfp >> 1 == i:
+ self.next_arg_svfp = self.next_arg_vfp << 1
+ lst = r.vfp_argument_regs
+ try:
+ return lst[i]
+ except IndexError:
+ self.next_arg_vfp = self.next_arg_svfp = -1
+ return None
+
def prepare_arguments(self):
non_float_locs = []
non_float_regs = []
float_locs = []
float_regs = []
stack_args = []
+ singlefloats = None
arglocs = self.arglocs
argtypes = self.argtypes
count = 0 # stack alignment counter
on_stack = 0
- for arg in arglocs:
- if arg.type != FLOAT:
+ for i in range(len(arglocs)):
+ argtype = INT
+ if i < len(argtypes) and argtypes[i] == 'S':
+ argtype = argtypes[i]
+ arg = arglocs[i]
+ if arg.is_float():
+ argtype = FLOAT
+ reg = self.get_next_vfp(argtype)
+ if reg:
+ assert len(float_regs) < len(r.vfp_argument_regs)
+ float_locs.append(arg)
+ assert reg not in float_regs
+ float_regs.append(reg)
+ else: # float argument that needs to go on the stack
+ if count % 2 != 0:
+ stack_args.append(None)
+ count = 0
+ on_stack += 1
+ stack_args.append(arg)
+ on_stack += 2
+ elif argtype == 'S':
+ # Singlefloat argument
+ if singlefloats is None:
+ singlefloats = []
+ tgt = self.get_next_vfp(argtype)
+ if tgt:
+ singlefloats.append((arg, tgt))
+ else: # Singlefloat argument that needs to go on the stack
+ # treated the same as a regular core register argument
+ count += 1
+ on_stack += 1
+ stack_args.append(arg)
+ else:
if len(non_float_regs) < len(r.argument_regs):
reg = r.argument_regs[len(non_float_regs)]
non_float_locs.append(arg)
@@ -249,18 +310,6 @@
count += 1
on_stack += 1
stack_args.append(arg)
- else:
- if len(float_regs) < len(r.vfp_argument_regs):
- reg = r.vfp_argument_regs[len(float_regs)]
- float_locs.append(arg)
- float_regs.append(reg)
- else: # float argument that needs to go on the stack
- if count % 2 != 0:
- stack_args.append(None)
- count = 0
- on_stack += 1
- stack_args.append(arg)
- on_stack += 2
# align the stack
if count % 2 != 0:
stack_args.append(None)
@@ -275,13 +324,28 @@
non_float_locs.append(self.fnloc)
non_float_regs.append(r.r4)
self.fnloc = r.r4
+ # remap values stored in vfp registers
+ remap_frame_layout(self.asm, float_locs, float_regs, r.vfp_ip)
+ if singlefloats:
+ for src, dest in singlefloats:
+ if src.is_float():
+ assert 0, 'unsupported case'
+ if src.is_stack():
+ # use special VLDR for 32bit
+ self.asm.regalloc_mov(src, r.ip)
+ src = r.ip
+ if src.is_imm():
+ self.mc.gen_load_int(r.ip.value, src.value)
+ src = r.ip
+ if src.is_core_reg():
+ self.mc.VMOV_cs(dest.value, src.value)
# remap values stored in core registers
remap_frame_layout(self.asm, non_float_locs, non_float_regs, r.ip)
- # remap values stored in vfp registers
- remap_frame_layout(self.asm, float_locs, float_regs, r.vfp_ip)
def load_result(self):
resloc = self.resloc
+ if self.restype == 'S':
+ self.mc.VMOV_sc(resloc.value, r.s0.value)
# ensure the result is wellformed and stored in the correct location
if resloc is not None and resloc.is_core_reg():
self._ensure_result_bit_extension(resloc,
diff --git a/rpython/jit/backend/arm/codebuilder.py b/rpython/jit/backend/arm/codebuilder.py
--- a/rpython/jit/backend/arm/codebuilder.py
+++ b/rpython/jit/backend/arm/codebuilder.py
@@ -178,6 +178,30 @@
| (dm & 0xF))
self.write32(instr)
+ def VMOV_sc(self, dest, src):
+ """move a single precision vfp register[src] to a core reg[dest]"""
+ self._VMOV_32bit(src, dest, to_arm_register=1)
+
+ def VMOV_cs(self, dest, src):
+ """move a core register[src] to a single precision vfp
+ register[dest]"""
+ self._VMOV_32bit(dest, src, to_arm_register=0)
+
+ def _VMOV_32bit(self, float_reg, core_reg, to_arm_register, cond=cond.AL):
+ """This instruction transfers the contents of a single-precision VFP
+ register to an ARM core register, or the contents of an ARM core
+ register to a single-precision VFP register.
+ """
+ instr = (cond << 28
+ | 0xE << 24
+ | to_arm_register << 20
+ | ((float_reg >> 1) & 0xF) << 16
+ | core_reg << 12
+ | 0xA << 8
+ | (float_reg & 0x1) << 7
+ | 1 << 4)
+ self.write32(instr)
+
def VMOV_cc(self, dd, dm, cond=cond.AL):
sz = 1 # for 64-bit mode
instr = (cond << 28
@@ -198,8 +222,16 @@
self._VCVT(target, source, cond, 0, 1)
def _VCVT(self, target, source, cond, opc2, sz):
- D = 0
- M = 0
+ # A8.6.295
+ to_integer = (opc2 >> 2) & 1
+ if to_integer:
+ D = target & 1
+ target >>= 1
+ M = (source >> 4) & 1
+ else:
+ M = source & 1
+ source >>= 1
+ D = (target >> 4) & 1
op = 1
instr = (cond << 28
| 0xEB8 << 16
@@ -216,8 +248,8 @@
def _VCVT_single_double(self, target, source, cond, sz):
# double_to_single = (sz == '1');
- D = 0
- M = 0
+ D = target & 1 if sz else (target >> 4) & 1
+ M = (source >> 4) & 1 if sz else source & 1
instr = (cond << 28
| 0xEB7 << 16
| 0xAC << 4
diff --git a/rpython/jit/backend/arm/locations.py b/rpython/jit/backend/arm/locations.py
--- a/rpython/jit/backend/arm/locations.py
+++ b/rpython/jit/backend/arm/locations.py
@@ -55,12 +55,8 @@
type = FLOAT
width = 2 * WORD
- def get_single_precision_regs(self):
- return [VFPRegisterLocation(i) for i in
- [self.value * 2, self.value * 2 + 1]]
-
def __repr__(self):
- return 'vfp%d' % self.value
+ return 'vfp(d%d)' % self.value
def is_core_reg(self):
return False
@@ -74,6 +70,14 @@
def is_float(self):
return True
+class SVFPRegisterLocation(VFPRegisterLocation):
+ """Single Precission VFP Register"""
+ _immutable_ = True
+ width = WORD
+ type = 'S'
+
+ def __repr__(self):
+ return 'vfp(s%d)' % self.value
class ImmLocation(AssemblerLocation):
_immutable_ = True
diff --git a/rpython/jit/backend/arm/opassembler.py b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -1102,17 +1102,16 @@
arg, res = arglocs
assert arg.is_vfp_reg()
assert res.is_core_reg()
- self.mc.VCVT_float_to_int(r.vfp_ip.value, arg.value)
- self.mc.VMOV_rc(res.value, r.ip.value, r.vfp_ip.value)
+ self.mc.VCVT_float_to_int(r.svfp_ip.value, arg.value)
+ self.mc.VMOV_sc(res.value, r.svfp_ip.value)
return fcond
def emit_op_cast_int_to_float(self, op, arglocs, regalloc, fcond):
arg, res = arglocs
assert res.is_vfp_reg()
assert arg.is_core_reg()
- self.mc.MOV_ri(r.ip.value, 0)
- self.mc.VMOV_cr(res.value, arg.value, r.ip.value)
- self.mc.VCVT_int_to_float(res.value, res.value)
+ self.mc.VMOV_cs(r.svfp_ip.value, arg.value)
+ self.mc.VCVT_int_to_float(res.value, r.svfp_ip.value)
return fcond
emit_op_llong_add = gen_emit_float_op('llong_add', 'VADD_i64')
@@ -1147,15 +1146,14 @@
arg, res = arglocs
assert arg.is_vfp_reg()
assert res.is_core_reg()
- self.mc.VCVT_f64_f32(r.vfp_ip.value, arg.value)
- self.mc.VMOV_rc(res.value, r.ip.value, r.vfp_ip.value)
+ self.mc.VCVT_f64_f32(r.svfp_ip.value, arg.value)
+ self.mc.VMOV_sc(res.value, r.svfp_ip.value)
return fcond
def emit_op_cast_singlefloat_to_float(self, op, arglocs, regalloc, fcond):
arg, res = arglocs
assert res.is_vfp_reg()
assert arg.is_core_reg()
- self.mc.MOV_ri(r.ip.value, 0)
- self.mc.VMOV_cr(res.value, arg.value, r.ip.value)
- self.mc.VCVT_f32_f64(res.value, res.value)
+ self.mc.VMOV_cs(r.svfp_ip.value, arg.value)
+ self.mc.VCVT_f32_f64(res.value, r.svfp_ip.value)
return fcond
diff --git a/rpython/jit/backend/arm/registers.py b/rpython/jit/backend/arm/registers.py
--- a/rpython/jit/backend/arm/registers.py
+++ b/rpython/jit/backend/arm/registers.py
@@ -1,8 +1,10 @@
from rpython.jit.backend.arm.locations import VFPRegisterLocation
+from rpython.jit.backend.arm.locations import SVFPRegisterLocation
from rpython.jit.backend.arm.locations import RegisterLocation
registers = [RegisterLocation(i) for i in range(16)]
vfpregisters = [VFPRegisterLocation(i) for i in range(16)]
+svfpregisters = [SVFPRegisterLocation(i) for i in range(32)]
[r0, r1, r2, r3, r4, r5, r6, r7,
r8, r9, r10, r11, r12, r13, r14, r15] = registers
@@ -10,6 +12,10 @@
[d0, d1, d2, d3, d4, d5, d6, d7,
d8, d9, d10, d11, d12, d13, d14, d15] = vfpregisters
+# single precission VFP registers, 32-bit
+for i in range(32):
+ globals()['s%d' % i] = svfpregisters[i]
+
# aliases for registers
fp = r11
ip = r12
@@ -17,6 +23,7 @@
lr = r14
pc = r15
vfp_ip = d15
+svfp_ip = s31
all_regs = [r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10]
all_vfp_regs = vfpregisters[:-1]
@@ -27,6 +34,7 @@
callee_restored_registers = callee_resp + [pc]
vfp_argument_regs = caller_vfp_resp = [d0, d1, d2, d3, d4, d5, d6, d7]
+svfp_argument_regs = [globals()['s%i' % i] for i in range(16)]
callee_vfp_resp = [d8, d9, d10, d11, d12, d13, d14, d15]
callee_saved_vfp_registers = callee_vfp_resp
diff --git a/rpython/jit/backend/arm/runner.py b/rpython/jit/backend/arm/runner.py
--- a/rpython/jit/backend/arm/runner.py
+++ b/rpython/jit/backend/arm/runner.py
@@ -22,7 +22,7 @@
supports_floats = True
supports_longlong = False # XXX requires an implementation of
# read_timestamp that works in user mode
- supports_singlefloats = not detect_hardfloat()
+ supports_singlefloats = True
from rpython.jit.backend.arm.arch import JITFRAME_FIXED_SIZE
all_reg_indexes = range(len(all_regs))
diff --git a/rpython/rlib/rdynload.py b/rpython/rlib/rdynload.py
--- a/rpython/rlib/rdynload.py
+++ b/rpython/rlib/rdynload.py
@@ -4,7 +4,6 @@
from rpython.rtyper.tool import rffi_platform
from rpython.rtyper.lltypesystem import rffi
from rpython.rlib.rarithmetic import r_uint
-from rpython.rlib.objectmodel import we_are_translated
from rpython.translator.tool.cbuild import ExternalCompilationInfo
from rpython.translator.platform import platform
@@ -80,38 +79,6 @@
RTLD_NOW = cConfig.RTLD_NOW
RTLD_LAZY = cConfig.RTLD_LAZY
- _t_opened = {}
-
- def t_dlopen(name):
- # for direct execution: can't use the regular way on FreeBSD :-(
- # http://factor-language.blogspot.de/2009/02/note-about-libdl-functions-on-netbsd.html
- import ctypes
- if name:
- name = rffi.charp2str(name)
- else:
- name = None
- try:
- res = ctypes.cdll.LoadLibrary(name)
- except OSError, e:
- raise DLOpenError(str(e))
- h = rffi.cast(rffi.VOIDP, res._handle)
- _t_opened[rffi.cast(rffi.LONG, h)] = res
- return h
-
- def t_dlclose(handle):
- _t_opened.pop(rffi.cast(rffi.LONG, handle))
- return rffi.cast(rffi.INT, 0)
-
- def t_dldym(handle, name):
- import ctypes
- lib = _t_opened[rffi.cast(rffi.LONG, handle)]
- try:
- symbol = lib[name]
- except AttributeError:
- raise KeyError(name)
- res = ctypes.cast(symbol, ctypes.c_void_p)
- return rffi.cast(rffi.VOIDP, res.value or 0)
-
def dlerror():
# XXX this would never work on top of ll2ctypes, because
# ctypes are calling dlerror itself, unsure if I can do much in this
@@ -124,8 +91,6 @@
def dlopen(name, mode=-1):
""" Wrapper around C-level dlopen
"""
- if not we_are_translated():
- return t_dlopen(name)
if mode == -1:
if RTLD_LOCAL is not None:
mode = RTLD_LOCAL
@@ -139,16 +104,11 @@
raise DLOpenError(err)
return res
- def dlclose(handle):
- if not we_are_translated():
- return t_dlclose(handle)
- return c_dlclose(handle)
+ dlclose = c_dlclose
def dlsym(libhandle, name):
""" Wrapper around C-level dlsym
"""
- if not we_are_translated():
- return t_dldym(libhandle, name)
res = c_dlsym(libhandle, name)
if not res:
raise KeyError(name)
diff --git a/rpython/rlib/test/test_rdynload.py b/rpython/rlib/test/test_rdynload.py
--- a/rpython/rlib/test/test_rdynload.py
+++ b/rpython/rlib/test/test_rdynload.py
@@ -21,4 +21,3 @@
lltype.Signed)), dlsym(lib, 'abs'))
assert 1 == handle(1)
assert 1 == handle(-1)
- dlclose(lib)
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