[pypy-commit] pypy gc_no_cleanup_nursery: Enough to pass test_zero_array. Still missing the short-size optimization.

[arigo]

Author: Armin Rigo <arigo at tunes.org>
Branch: gc_no_cleanup_nursery
Changeset: r73677:ec9889b7a5a1
Date: 2014-09-24 16:12 +0000
http://bitbucket.org/pypy/pypy/changeset/ec9889b7a5a1/

Log:	Enough to pass test_zero_array. Still missing the short-size
	optimization.

diff --git a/rpython/jit/backend/arm/opassembler.py b/rpython/jit/backend/arm/opassembler.py
--- a/rpython/jit/backend/arm/opassembler.py
+++ b/rpython/jit/backend/arm/opassembler.py
@@ -25,7 +25,7 @@
 from rpython.jit.backend.llsupport.descr import InteriorFieldDescr
 from rpython.jit.backend.llsupport.assembler import GuardToken, BaseAssembler
 from rpython.jit.backend.llsupport.regalloc import get_scale
-from rpython.jit.metainterp.history import (Box, AbstractFailDescr,
+from rpython.jit.metainterp.history import (Box, AbstractFailDescr, ConstInt,
                                             INT, FLOAT, REF)
 from rpython.jit.metainterp.history import TargetToken
 from rpython.jit.metainterp.resoperation import rop
@@ -1175,3 +1175,76 @@
         self.mc.VMOV_cs(r.svfp_ip.value, arg.value)
         self.mc.VCVT_f32_f64(res.value, r.svfp_ip.value)
         return fcond
+
+    #from ../x86/regalloc.py:1388
+    def emit_op_zero_array(self, op, arglocs, regalloc, fcond):
+        from rpython.jit.backend.llsupport.descr import unpack_arraydescr
+        assert len(arglocs) == 0
+        itemsize, baseofs, _ = unpack_arraydescr(op.getdescr())
+        args = op.getarglist()
+        base_loc = regalloc.rm.make_sure_var_in_reg(args[0], args)
+        sibox = args[1]
+        if isinstance(sibox, ConstInt):
+            startindex_loc = None
+            startindex = sibox.getint()
+            assert startindex >= 0
+        else:
+            startindex_loc = regalloc.rm.make_sure_var_in_reg(sibox, args)
+            startindex = -1
+        length_box = op.getarg(2)
+        if isinstance(length_box, ConstInt):
+            constbytes = length_box.getint() * itemsize
+        else:
+            constbytes = -1
+        if 0 <= constbytes <= 56 and (0):
+                #valid_addressing_size(itemsize) or
+                #(isinstance(startindex_loc, ImmedLoc) and
+                #  startindex_loc.value == 0)):
+            XXX
+        else:
+            # base_loc and startindex_loc are in two regs here (or they are
+            # immediates).  Compute the dstaddr_loc, which is the raw
+            # address that we will pass as first argument to memset().
+            # It can be in the same register as either one, but not in
+            # args[2], because we're still needing the latter.
+            dstaddr_box = TempBox()
+            dstaddr_loc = regalloc.rm.force_allocate_reg(dstaddr_box, [args[2]])
+            if startindex >= 0:    # a constant
+                ofs = baseofs + startindex * itemsize
+                reg = base_loc.value
+            else:
+                self.mc.gen_load_int(r.ip.value, itemsize)
+                self.mc.MLA(dstaddr_loc.value, r.ip.value,
+                            startindex_loc.value, base_loc.value)
+                ofs = baseofs
+                reg = dstaddr_loc.value
+            if check_imm_arg(ofs):
+                self.mc.ADD_ri(dstaddr_loc.value, reg, imm=ofs)
+            else:
+                self.mc.gen_load_int(r.ip.value, ofs)
+                self.mc.ADD_rr(dstaddr_loc.value, reg, r.ip.value)
+            #
+            if constbytes >= 0:
+                length_loc = imm(constbytes)
+            else:
+                # load length_loc in a register different than dstaddr_loc
+                length_loc = regalloc.rm.make_sure_var_in_reg(length_box,
+                                                              [dstaddr_box])
+                if itemsize > 1:
+                    # we need a register that is different from dstaddr_loc,
+                    # but which can be identical to length_loc (as usual,
+                    # only if the length_box is not used by future operations)
+                    bytes_box = TempBox()
+                    bytes_loc = regalloc.rm.force_allocate_reg(bytes_box,
+                                                               [dstaddr_box])
+		    self.mc.gen_load_int(r.ip.value, itemsize)
+                    self.mc.MUL(bytes_loc.value, r.ip.value, length_loc.value)
+                    length_box = bytes_box
+                    length_loc = bytes_loc
+            #
+            # call memset()
+            regalloc.before_call()
+            self.simple_call_no_collect(imm(self.memset_addr),
+                                        [dstaddr_loc, imm(0), length_loc])
+            regalloc.rm.possibly_free_var(length_box)
+            regalloc.rm.possibly_free_var(dstaddr_box)
diff --git a/rpython/jit/backend/arm/regalloc.py b/rpython/jit/backend/arm/regalloc.py
--- a/rpython/jit/backend/arm/regalloc.py
+++ b/rpython/jit/backend/arm/regalloc.py
@@ -996,6 +996,7 @@
 
     prepare_op_copystrcontent = void
     prepare_op_copyunicodecontent = void
+    prepare_op_zero_array = void
 
     def prepare_op_unicodelen(self, op, fcond):
         l0 = self.make_sure_var_in_reg(op.getarg(0))