[pypy-dev] JIT improvements for RISC processors

[Michael Hudson]

I was kind of hoping you would be in #pypy sometime in the last couple
of days to talk about this.

"Fabrizio Milo aka misto" <mistobaan at gmail.com> writes:

> Hi to everyone,
>
> I am really interested in code machine generation for risc processors.
> In order to have an idea of the work that can be done, and to create
> a proposal I will ask some questions:
>
> - What is already done? where is it? (paths, file names please)

Well, the code generation code is all in pypy.jit.codegen;
pypy.jit.codegen.model is a good starting place.

There is a somewhat complete x86 backend and a less complete PowerPC
backend (although I'm working on that right now and it will maybe have
caught up by the end of the week, in terms of functionality at least).

> - What ideas are already defined and need just to be implemented?

Well, the interface in the model file just referenced is more or less
defined, although there are a few details that it would be good to
change to make decent register allocation possible.

> - Material that I have to / should read?
>
> I have a rough background on RISC assembler,
> the most comes from MIPS and IBM's PowerPC
>
> some material I am aware of is http://tinyurl.com/9dw43

Also worth reading are IBM's "Compiler Writer's Guide" and Apple's
"LowLevelABI.pdf":

http://www-306.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF7785256996007558C6

http://gemma.apple.com/documentation/developertools/Conceptual/LowLevelABI/LowLevelABI.pdf

For a Summer of PyPy project there needs to be some reasonably clearly
defined goals.  An obvious and useful target is improving the quality
of the generated PowerPC code -- I'm making it work at the moment, I'm
certainly not making it fast.  Another good thing would be sharing
some code between the PPC and x86 code generation (not so much the
actual code generation, but there are things about memory management
of code buffers and so on that are likely to be similar between any
machine code backend).  And once this is done, adding another backend
for say MIPS should be reasonably straightforward.

Cheers,
mwh

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